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| t-sminti 4b3 t s econd gen. m odular i sdn nt ( i ntelligent) pef 82902 version 1.1 data sheet, ds 1, nov. 2001 wired communications never stop thinking.
edition 2001-11-09 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. wired communications t-sminti 4b3 t s econd gen. m odular i sdn nt ( i ntelligent) pef 82902 version 1.1 data sheet, ds 1, nov. 2001 never stop thinking. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com pef 82902 revision history: 2001-11-09 ds 1 previous version: preliminary data sheet 06.01 page subjects (major changes since last revision) table 18 figure 41 chapter 2.4.7.4 additional c/i-command ltd chapter 3.2.3 chapter 4.3 chapter 4.9.4 the framer / deframer loopback (dlb) is no more supported chapter 4.3 reset value of masku is ffh (not 00h) chapter 4.3 chapter 4.9.8 reset value of fw-version is 3eh chapter 4.9.4 restriction of loop.lb1, lb2 and lbbd to transparent state chapter 5.2 input leakage current ain, bin: max. 30a chapter 5.4 reduced power consumption pef 82902 table of contents page data sheet 2001-11-09 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 not supported are ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.6 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6.1 specific pins and test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.7 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 microcontroller interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.1 serial control interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.1.1 programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1.2 parallel microcontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.1.3 microcontroller clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.1 iom?-2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.2 iom?-2 handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3.2.1 controller data access (cda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.3.2.2 serial data strobe signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.3.3 iom?-2 monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.3.1 handshake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3.3.2 error treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.3.3.3 monitor channel programming as a master device . . . . . . . . . . . 47 2.3.3.4 monitor channel programming as a slave device . . . . . . . . . . . . 47 2.3.3.5 monitor time-out procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.3.3.6 monitor interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.3.4 c/i channel handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.3.5 d-channel access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3.5.1 application examples for d-channel access control . . . . . . . . . . . . 51 2.3.5.2 tic bus handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.3.5.3 stop/go bit handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.3.5.4 d-channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3.5.5 state machine of the d-channel arbiter . . . . . . . . . . . . . . . . . . . . . . 55 2.3.6 activation/deactivation of iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . 57 2.4 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.4.1 4b3t frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.4.2 maintenance channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.3 coding from binary to ternary data . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.4.4 decoding from ternary to binary data . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.4.4.1 monitoring of code violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 pef 82902 table of contents page data sheet 2001-11-09 2.4.4.2 block error counter (rds error counter) . . . . . . . . . . . . . . . . . . . . . 65 2.4.5 scrambler / descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.6 command/indication codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.4.7 state machine for activation and deactivation . . . . . . . . . . . . . . . . . . . 67 2.4.7.1 state machine notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.4.7.2 awake protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.4.7.3 nt state machine (iec-t / ntc-t compatible) . . . . . . . . . . . . . . . . 71 2.4.7.4 inputs to the u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.4.7.5 outputs of the u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 2.4.7.6 nt-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.4.8 u-transceiver interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 2.5 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.5.1 line coding, frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 2.5.2 s/q channels, multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.5.3 data transfer between iom?-2 and s0 . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.5.4 loopback 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.5.5 control of s-transceiver / state machine . . . . . . . . . . . . . . . . . . . . . . . 82 2.5.5.1 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2.5.5.2 state machine nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 2.5.5.3 state machine lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2.5.6 s-transceiver enable / disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 2.5.7 interrupt structure s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.1 layer 1 activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.1.1 generation of 4b3t signal elements . . . . . . . . . . . . . . . . . . . . . . . . . . 96 3.1.2 complete activation initiated by exchange . . . . . . . . . . . . . . . . . . . . . . 99 3.1.3 complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.1.4 complete activation initiated by nt . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.1.5 complete deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 3.1.6 loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 3.2 layer 1 loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.2.1 analog loop-back s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 3.2.2 loopback no.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.2.2.1 complete loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.2.2.2 loopback no.2 - single channel loopbacks . . . . . . . . . . . . . . . . . . 106 3.2.3 local loopbacks featured by the loop register . . . . . . . . . . . . . . . 106 3.3 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.3.1 power supply blocking recommendation . . . . . . . . . . . . . . . . . . . . . . 108 3.3.2 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.3.3 s-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 3.3.4 oscillator circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.3.5 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 pef 82902 table of contents page data sheet 2001-11-09 4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.1 address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.3 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.3.1 reset of u-transceiver functions during deactivation or with c/i-code reset 122 4.3.2 mode register evaluation timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 4.4 detailed c/i registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.4.1 modeh - mode register iom-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 4.4.2 cir0 - command/indication receive 0 . . . . . . . . . . . . . . . . . . . . . . . . 124 4.4.3 cix0 - command/indication transmit 0 . . . . . . . . . . . . . . . . . . . . . . . . 126 4.4.4 cir1 - command/indication receive 1 . . . . . . . . . . . . . . . . . . . . . . . . 126 4.4.5 cix1 - command/indication transmit 1 . . . . . . . . . . . . . . . . . . . . . . . . 127 4.5 detailed s-transceiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 4.5.1 s_conf0 - s-transceiver configuration register 0 . . . . . . . . . . . . . . 128 4.5.2 s_conf2 - s-transmitter configuration register 2 . . . . . . . . . . . . . . 129 4.5.3 s_sta - s-transceiver status register . . . . . . . . . . . . . . . . . . . . . . . 129 4.5.4 s_cmd - s-transceiver command register . . . . . . . . . . . . . . . . . . . . 130 4.5.5 sqrr - s/q-channel receive register . . . . . . . . . . . . . . . . . . . . . . . 131 4.5.6 sqxr- s/q-channel transmit register . . . . . . . . . . . . . . . . . . . . . . . 132 4.5.7 istas - interrupt status register s-transceiver . . . . . . . . . . . . . . . . . 133 4.5.8 masks - mask s-transceiver interrupt . . . . . . . . . . . . . . . . . . . . . . . . 134 4.5.9 s_mode - s-transceiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 4.6 interrupt and general configuration registers . . . . . . . . . . . . . . . . . . . . 135 4.6.1 ista - interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 4.6.2 mask - mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 4.6.3 mode1 - mode1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 4.6.4 mode2 - mode2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.6.5 id - identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 4.6.6 sres - software reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.7 detailed iom ? -2 handler registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 4.7.1 cdaxy - controller data access register xy . . . . . . . . . . . . . . . . . . . . 140 4.7.2 xxx_tsdpxy - time slot and data port selection for chxy . . . . . . . 141 4.7.3 cdax_cr - control register controller data access ch1x . . . . . . . . 142 4.7.4 s_cr - control register s-transceiver data . . . . . . . . . . . . . . . . . . . 143 4.7.5 ci_cr - control register for ci1 data . . . . . . . . . . . . . . . . . . . . . . . . 144 4.7.6 mon_cr - control register monitor data . . . . . . . . . . . . . . . . . . . . . 145 4.7.7 sds1_cr - control register serial data strobe 1 . . . . . . . . . . . . . . . 146 4.7.8 sds2_cr - control register serial data strobe 2 . . . . . . . . . . . . . . . 147 4.7.9 iom_cr - control register iom data . . . . . . . . . . . . . . . . . . . . . . . . . 148 4.7.10 mcda - monitoring cda bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 4.7.11 sti - synchronous transfer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . 149 pef 82902 table of contents page data sheet 2001-11-09 4.7.12 asti - acknowledge synchronous transfer interrupt . . . . . . . . . . . . . 150 4.7.13 msti - mask synchronous transfer interrupt . . . . . . . . . . . . . . . . . . . 151 4.8 detailed monitor handler registers . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.8.1 mor - monitor receive channel . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.8.2 mox - monitor transmit channel . . . . . . . . . . . . . . . . . . . . . . . . . . 152 4.8.3 mosr - monitor interrupt status register . . . . . . . . . . . . . . . . . . . 152 4.8.4 mocr - monitor control register . . . . . . . . . . . . . . . . . . . . . . . . . . 153 4.8.5 msta - monitor status register . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 4.8.6 mconf - monitor configuration register . . . . . . . . . . . . . . . . . . . . 154 4.9 detailed u-transceiver registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.9.1 opmode - operation mode register . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.9.2 ucir - c/i code read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.9.3 uciw - c/i code write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 4.9.4 loop - loopback register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 4.9.5 rds - block error counter register . . . . . . . . . . . . . . . . . . . . . . . . . . 157 4.9.6 istau - interrupt status register u-interface . . . . . . . . . . . . . . . . . . . 157 4.9.7 masku - mask register u-interface . . . . . . . . . . . . . . . . . . . . . . . . . . 158 4.9.8 fw_version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 5.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 5.3 capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.5 supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 5.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 5.6.1 iom ? -2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 5.6.2 serial p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 5.6.3 parallel p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 5.6.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 5.6.5 undervoltage detection characteristics . . . . . . . . . . . . . . . . . . . . . . . 174 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7 appendix: differences between q- and t-smint?i . . . . . . . . . . . . . . . 178 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.1.1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.1.2 led pin act . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 7.2 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.2.1 u-interface conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 7.2.2 u-transceiver state machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 7.2.3 command/indication codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 7.2.4 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 7.2.5 register summary u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 pef 82902 page data sheet 2001-11-09 table of contents 7.3 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 8 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 pef 82902 list of figures page data sheet 2001-11-09 figure 1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3 application example t-smint ? i: high feature intelligent nt. . . . . . . 13 figure 4 control via p interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5 control via iom?-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6 serial control interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7 serial command structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8 direct/indirect register address mode . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 9 reset generation of the t-smint?i . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10 iom ? -2 frame structure of the t-smint?i . . . . . . . . . . . . . . . . . . . . . 27 figure 11 architecture of the iom?-2 handler . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12 data access via cdax0 and cdax1 register pairs . . . . . . . . . . . . . . . 31 figure 13 examples for data access via cdaxy registers. . . . . . . . . . . . . . . . . 32 figure 14 data access when looping tsa from du to dd . . . . . . . . . . . . . . . . . 33 figure 15 data access when shifting tsa to tsb on du (dd) . . . . . . . . . . . . . . 34 figure 16 example for monitoring data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 17 interrupt structure of the synchronous data transfer . . . . . . . . . . . . . 38 figure 18 examples for the synchronous transfer interrupt control with one stixy enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19 data strobe signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 20 monitor channel protocol (iom?-2) . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 21 monitor channel, transmission abort requested by the receiver. . . . 46 figure 22 monitor channel, transmission abort requested by the transmitter. . 46 figure 23 monitor channel, normal end of transmission . . . . . . . . . . . . . . . . . . 46 figure 24 monitor interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 25 cic interrupt structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 26 d-channel arbitration: c with hdlc and direct access to tic bus . 51 figure 27 d-channel arbitration: c with hdlc and no access to tic bus . . . . 52 figure 28 structure of last octet of ch2 on du . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 29 structure of last octet of ch2 on dd . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 30 state machine of the d-channel arbiter (simplified view). . . . . . . . . . 56 figure 31 deactivation of the iom ? -2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 32 state diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 33 awake procedure initiated by the lt . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 34 awake procedure initiated by the nt. . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 35 nt state machine (iec-t/ntc-t compatible). . . . . . . . . . . . . . . . . . . 71 figure 36 interrupt structure u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 37 s/t -interface line code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 38 frame structure at reference points s and t (itu i.430). . . . . . . . . . 80 figure 39 s-transceiver control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 40 state diagram notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 41 state machine nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 pef 82902 list of figures page data sheet 2001-11-09 figure 42 state machine lt-s mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 43 interrupt structure s-transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 44 activation initiated by exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 45 activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 46 activation initiated by nt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 47 complete deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 48 loop 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 49 test loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 50 external loop at the s/t-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 51 complete loopback options in nt-mode . . . . . . . . . . . . . . . . . . . . . 106 figure 52 loopbacks featured by register loop . . . . . . . . . . . . . . . . . . . . . . 107 figure 53 power supply blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 54 external circuitry u-transceiver with external hybrid . . . . . . . . . . . . 109 figure 55 external circuitry s-interface transmitter . . . . . . . . . . . . . . . . . . . . . 112 figure 56 external circuitry s-interface receiver . . . . . . . . . . . . . . . . . . . . . . . 112 figure 57 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 58 address space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 59 t-smint?i interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 60 maximum sinusoidal ripple on supply voltage . . . . . . . . . . . . . . . 164 figure 61 input/output waveform for ac tests. . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 62 iom?-2 interface - bit synchronization timing . . . . . . . . . . . . . . . . . 166 figure 63 iom ? -2 interface - frame synchronization timing . . . . . . . . . . . . . . 166 figure 64 serial control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 figure 65 microprocessor read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 66 microprocessor write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 67 multiplexed address timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 figure 68 non-multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 69 microprocessor read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 70 microprocessor write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 figure 71 non-multiplexed address timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 72 reset input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 figure 73 undervoltage control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 figure 74 ntc-q compatible state machine q-smint?i: 2b1q . . . . . . . . . . . . 181 figure 75 simplified state machine q-smint?i: 2b1q . . . . . . . . . . . . . . . . . . . 182 figure 76 iec-t/ntc-t compatible state machine t-smint?i: 4b3t. . . . . . . . 183 figure 77 interrupt structure u-transceiver q-smint?i: 2b1q . . . . . . . . . . . . . 185 figure 78 interrupt structure u-transceiver t-smint?i: 4b3t. . . . . . . . . . . . . . 186 figure 79 external circuitry q- and t-smint?i . . . . . . . . . . . . . . . . . . . . . . . . . 190 pef 82902 list of tables page data sheet 2001-11-09 table 1 nt products of the 2nd generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3 act states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4 interface selection for the t-smint?i. . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5 header byte code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6 bus operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7 mclk frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8 reset source selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9 examples for synchronous transfer interrupts . . . . . . . . . . . . . . . . . . 37 table 10 transmit direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 11 receive direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 12 t-smint?i configuration settings in intelligent nt applications . . . . . 55 table 13 frame structure a for downstream transmission lt to nt . . . . . . . . 61 table 14 frame structure b for upstream transmission nt to lt. . . . . . . . . . . 62 table 15 mms 43 coding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 16 4b3t decoding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 17 active states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 18 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 19 differences to the former nt-sm of the iec-t/ntc-t. . . . . . . . . . . . . 72 table 20 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 21 m symbol output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 22 signal output on uk0 in state test . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 23 c/i-code output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 24 s/q-bit position identification and multi-frame structure . . . . . . . . . . 81 table 25 4b3t signal elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 26 generation of the 4b3t signal elements. . . . . . . . . . . . . . . . . . . . . . . 97 table 27 s/t-interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 28 u-transformer parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 29 s-transformer parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 30 crystal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 31 reset of u-transceiver functions during deactivation or with c/i-code reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 32 mode register with immediate evaluation and execution. . . . . . . . . 123 table 33 maximum input currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 34 s-transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 35 u-transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 table 36 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 table 37 reset input signal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 38 parameters of the uvd/por circuit . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 39 design number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 41 act states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 pef 82902 overview data sheet 1 2001-11-09 1 overview the peb 82902 (t-smint i) offers u-transceiver, s-transceiver and an iom -2 interface. a microcontroller interface provides access to both transceivers as well as the iom -2 interface. however, as opposed to its bigger brother t-smint ix, the t-smint i does not have an hdlc controller. main target applications of the t-smint i are intelligent nt applications where the hdlc controller(s) is (are) provided by the microcontroller. an example for such a microcontroller is the infineon utah chip which features four flexible hdlc controllers. table 1 on page 1 summarizes the 2nd generation nt products. table 1 nt products of the 2nd generation pef 80902 pef 81902 pef 82902 t-smint ? ot-smint ? ix t-smint ? i package p-mqfp-44 p-mqfp-64 p-tqfp-64 p-mqfp-64 p-tqfp-64 register access no u+s+hdlc+ iom ?2 u+s+iom ?2 access via n.a parallel (or sci or iom ?2 ) parallel (or sci or iom ?2 ) mclk, watchdog timer, sds, bcl, d- channel arbitration, iom ?2 access and manipulation etc. provided no yes yes hdlc controller no yes no nt1 mode available yes (only) no no pef 82902 overview data sheet 2 2001-11-09 1.1 references [1] ts 102 080, transmission and multiplexing; isdn basic rate access; digital transmission system on metallic local lines, etsi, november 1998 [2] ftz 1 tr 220 technische richtlinie, spezifikation der isdn schnittstelle uk0 schicht 1, deutsche telecom ag, august 1991 [3] ts 0284/96 technische spezifikation intelligenter netzabschlu? (int) mit den funktionen eines terminaladapters ta 2a/b (ohne internverkehr), deutsche telekom ag, m?rz 2001 [4] pr ets 300 012 draft, isdn; basic user network interface (uni), etsi, november 1996 [5] t1.605-1991, isdn-basic access interface for s and t reference points (layer 1 specification), ansi, 1991 [6] i.430, isdn user-network interfaces: layer 1 recommendations, itu, november 1988 [7] iec-t, isdn echocancellation circuit, peb 20901 (iec - td) / peb 20902 (iec - ta), preliminary target specification 11.88, siemens ag, 1988 [8] sbcx, s/t bus interface circuit extended, peb 2081 v3.4, user?s manual 11.96, siemens ag, 1996 [9] ntc-t, network termination controller (4b3t), peb 8090 v1.1, data sheet 06.98, siemens ag, 1998 [10] intc-q, intelligent network termination controller (2b1q), peb 8191 v1.1, data sheet 10.97, siemens ag, 1997 [11] q-sminto, 2b1 q s econd gen. m odular i sdn nt (o rdinary), pef 80912 q-smintix, 2b1 q s econd gen. m odular i sdn nt (i ntelligent e x ended), pef 81912 q-sminti, 2b1 q s econd gen. m odular i sdn nt (i ntelligent), pef 82912 v1.3, data sheets 03.01, infineon ag, 2001 [12] iom -2 interface reference guide, siemens ag, 03.91 [13] scout-s(x), siemens codec with s/t-transceiver, psb 2138x v1.1, preliminary data sheet 08.98, infineon technologies ag, 1999 [14] pita, pci interface for telephony/data applications v0.3, sican gmbh, september1997 [15] dual channel slicofi-2, hv-slic; duslic; peb3265, 4265, 4266; data sheet ds2, infineon technologies, july 2000. data sheet 3 2001-11-09 type package pef 82902 p-mqfp-64 pef 82902 p-tqfp-64 pef 82902 version 1.1 cmos p-mqfp-64-1,-2 p-tqfp-64-1 t-smint ? i 4b3t second gen. modular isdn nt (intelligent) 1.2 features features known from the peb 8090 u-transceiver and s-transceiver on one chip u-interface (4b3t) conform to etsi [1] and ftz [2]: ? meets all transmission requirements on all etsi and ftz loops with margin s/t-interface conform to etsi [4], ansi [5] and itu [6] ? supports point-to-point and bus configurations ? meets and exceeds all transmission requirements access to iom -2 c/i and monitor channels power-on reset and undervoltage detection with no external components esd robustness 2kv new features conforms to ? technische spezifikation intelligenter netzabschlu ? (int) mit den funktionen eines terminaladapters ta 2a/b ? of deutsche telekom ag [3] perfectly suited for high-end intelligent nts that require multiple hdlc controllers pin compatible with q-smint i (2nd generation) parallel or serial p-interface ? siemens/intel non-multiplexed (direct or indirect addressing (scout)) ? siemens/intel multiplexed ? motorola ? programmable mclk (can be disabled) (scout) pef 82902 overview data sheet 4 2001-11-09 enhanced iom ?2 interface ? timeslot access and manipulation (scout) ? bcl output; programmable and flexible strobes sds1/2, e.g. active during several timeslots. ? optional: all registers can be read and written to via new monitor channel concept ? external awake (eaw ) optional: implementation of s-transceiver statemachine in software power down and reset states (e.g. s-transceiver) for individual circuits automatic d-channel arbitration between s-bus and external hdlc controller priority setting (8/10) for off-chip hdlc controller pin vref and the according external capacitor removed inputs accept 3.3v and 5v i/o (open drain) accepts pull-up to 3.3v 1) lowest power consumption due to ? low power cmos technology (0.35) ? newly optimized low power libraries ? high output swing on u- and s-line interface leads to minimized power consumption ? single 3.3 volt power supply 1.3 not supported are ... no integrated hybrid is provided by the t-smint i. therefore, an external hybrid is always required, which consists of only two additional resistors as compared to an integrated hybrid, but allows for more flexibility in board design. on-chip hdlc controller auxiliary iom ?2 interface sra (capacitive receiver coupling is not suited for s-feeding) nt-star with star point on the iom ? -2 bus (already not supported in ntc-t). no access to s2-5 channels. access only to s1 and q channel as in scout-s. no selection betweeen transparent and non-auto mode provided. 1) pull-ups to 5v must be avoided. a so-called ? hot-electron-effect ? would lead to long term degradation. pef 82902 overview data sheet 5 2001-11-09 1.4 pin configuration figure 1 pin configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 /rsto vdda_sr vssa_sr /vdddet xout xin bout vdda_ux vssa_ux aout a5 s r 2 s r 1 v d d a _ s x v s s a _ s x t p 1 a 4 a 3 a 2 a 1 a 0 b c l d u d d fsc dcl a d 7 o r s d x a d 6 o r s d r a d 5 o r s c l k ad4 vssd vddd ad3 ad2 ad1 ad0 /eaw mclk /act v s s a _ u r v d d a _ u r a i n b i n / r s t v s s d v d d d a l e / w r o r r / w / r d o r / d s / c s / i n t s d s 2 s d s 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 s x 1 s x 2 t p 2 a6 pin_2.vsd t-smint ? i pef 82902 pef 82902 overview data sheet 6 2001-11-09 1.5 block diagram figure 2 block diagram clock generation s-transceiver u-tansceiver por/uvd factory tests iom-2 interface p interface (e.g. multiplexed mode) xin xout rst rsto aout bout ain bin tp2 sx2 sx1 sr2 sr1 tp1 led act eaw mclk int cs wr rd ale ad0-ad7 sds2 sds1 dd du bcl dcl fsc block diagram.vsd vdddet d-channel arbitration m o n c/i tic c d a w d t pef 82902 overview data sheet 7 2001-11-09 1.6 pin definitions and functions table 2 pin definitions and functions pin symbol type function 2 vdda_ur ? supply voltage for u-receiver (3.3 v 5%) 1 vssa_ur ? analog ground (0 v) u-receiver 62 vdda_ux ? supply voltage for u-transmitter (3.3 v 5%) 63 vssa_ux ? analog ground (0 v) u-transmitter 51 vdda_sr ? supply voltage for s-receiver (3.3 v 5%) 52 vssa_sr ? analog ground (0 v) s-receiver 46 vdda_sx ? supply voltage for s-transmitter (3.3 v 5%) 45 vssa_sx ? analog ground (0 v) s-transmitter 29 vddd ? supply voltage digital circuits (3.3 v 5%) 30 vssd ? ground (0 v) digital circuits 13 vddd ? supply voltage digital circuits (3.3 v 5%) 14 vssd ? ground (0 v) digital circuits 32 fsc o frame sync: 8-khz frame synchronization signal 31 dcl o data clock: iom -2 interface clock signal (double clock): 1.536 mhz 35 bcl o bit clock: the bit clock is identical to the iom -2 data rate (768 khz) 33 dd i/o od data downstream: data on the iom -2 interface 34 du i/o od data upstream: data on the iom -2 interface pef 82902 overview data sheet 8 2001-11-09 8 sds1 o serial data strobe1: programmable strobe signal for time slot and/or d-channel indication on iom -2 7 sds2 o serial data strobe2: programmable strobe signal for time slot and/or d-channel indication on iom -2 12 cs i chip select: a low level indicates a microcontroller access to the t-smint i 26 26 sclk ad5 i i/o serial clock: clock signal of the sci interface if a serial interface is selected multiplexed bus mode: address/data bus address/data line ad5 if the parallel interface is selected non-multiplexed bus mode: data bus data line d5 if the parallel interface is selected 27 27 sdr ad6 i i/o serial data receive: receive data line of the sci interface if a serial interface is selected multiplexed bus mode: address/data bus address/data line ad6 if the parallel interface is selected non-multiplexed bus mode: data bus data line d6 if the parallel interface is selected table 2 pin definitions and functions (cont ? d) pin symbol type function pef 82902 overview data sheet 9 2001-11-09 28 28 sdx ad7 od/o i/o serial data transmit: transmit data line of the sci interface if a serial interface is selected multiplexed bus mode: address/data bus address/data line ad7 if the parallel interface is selected non-multiplexed bus mode: data bus data line d7 if the parallel interface is selected 21 22 23 24 25 ad0 ad1 ad2 ad3 ad4 i/o i/o i/o i/o i/o multiplexed bus mode: address/data bus transfers addresses from the microcontroller to the t-smint i and data between the microcontroller and the t-smint i. non-multiplexed bus mode: data bus. transfers data between the microcontroller and the t-smint i (data lines d0-d4). 36 37 38 39 40 53 54 a0 a1 a2 a3 a4 a5 a6 i i i i i i i non-multiplexed bus mode: address bus transfers addresses from the microcontroller to the t-smint i. for indirect address mode only a0 is valid. multiplexed bus mode not used in multiplexed bus mode. in this case a0-a6 should directly be connected to vdd. 11 rd ds i i read indicates a read access to the registers (intel bus mode). data strobe the rising edge marks the end of a valid read or write operation (motorola bus mode). table 2 pin definitions and functions (cont ? d) pin symbol type function pef 82902 overview data sheet 10 2001-11-09 10 wr r/w i i write indicates a write access to the registers (intel bus mode). read/write a high identifies a valid host access as a read operation and a low identifies a valid host access as a write operation (motorola bus mode). 9 ale i address latch enable an address on the external address/data bus (multiplexed bus type only) is latched with the falling edge of ale. ale also selects the microcontroller interface type (multiplexed or non multiplexed). 5 rst i reset: low active reset input. schmitt-trigger input with hysteresis of typical 360mv. tie to ? 1 ? if not used. 6 rsto od reset output: low active reset output. 15 int od interrupt request: int becomes active if the t-smint i requests an interrupt. 18 mclk o microcontroller clock: clock output for the microcontroller 20 eaw i external awake : a low level on eaw during power down activates the clock generation of the t- smint i, i.e. the iom -2 interface provides fsc, dcl and bcl for read and write access. 1) 43 sx1 o s-bus transmitter output ( positive ) 44 sx2 o s-bus transmitter output ( negative ) 47 sr1 i s-bus receiver input table 2 pin definitions and functions (cont ? d) pin symbol type function pef 82902 overview data sheet 11 2001-11-09 48 sr2 i s-bus receiver input 60 xin i crystal 1: connected to a 15.36 mhz crystal 59 xout o crystal 2: connected to a 15.36 mhz crystal 64 aout o differential u-interface output 61 bout o differential u-interface output 3 ain i differential u-interface input 4 bin i differential u-interface input 49 vdddet i vdd detection: this pin selects if the v dd detection is active ( ? 0 ? ) and reset pulses are generated on pin rsto or whether it is deactivated ( ? 1 ? ) and an external reset has to be applied on pin rst. 17 act o activation led . indicates the activation status of u- and s- transceiver. can directly drive a led (4ma). 42 tp1 i test pin 1. used for factory device test. tie to ? v ss ? 50 tp2 i test pin 2. used for factory device test. tie to ? v ss ? 16, 19, 41, 55 tie to ? 1 ? 56, 57, 58 res reserved these pins are reserved for future use. do not connect. 1) this function of pin eaw is different to that defined in ref. [13] table 2 pin definitions and functions (cont ? d) pin symbol type function pef 82902 overview data sheet 12 2001-11-09 i: input o: output (push-pull) od: output (open drain) 1.6.1 specific pins and test modes led pin act a led can be connected to pin act to display four different states (off, slow flashing, fast flashing, on). it displays the activation status of the u- and s-transceiver according to table 3 . or it is programmable via two bits (led1 and led2 in register mode2). note: * denotes the duty cycle ?high? : ?low?. with: u_deactivated : ? deactivated state ? as defined in chapter 2.4.7.6 . u_activated : ? sbc synchronizing ? , ? wait for info u4h ? , and ? transparent ? as defined in chapter 2.4.7.6 . s-activated : ? activated state ? as defined in chapter 2.5.5.2 . note: optionally, pin act can drive a second led with inverse polarity (connect this additional led to 3.3v only). test modes the test patterns on the s-interface ( ? 2 khz single pulses ? , ? 96 khz continuous pulses ? ) and on the u-interface ( ? data through ? , ? send single pulses ? ,) are invoked via c/i codes (tm1, tm2, dt, ssp). setting sres.res_u to ? 1 ? forces the u-transceiver into test mode ? quiet mode ? (qm), i.e. the u-transceiver is hardware reset. table 3 act states pin act led u_deactivated u_activated s_activated v dd off 1 x x 2hz (1 : 1)* fast flashing 0 0 x 1hz (3 : 1)* slow flashing 0 1 0 gnd on 0 1 1 pef 82902 overview data sheet 13 2001-11-09 1.7 system integration figure 3 application example t-smint ? i: high feature intelligent nt the u-transceiver, the s-transceiver and the iom -2 channels can be controlled and monitored via: a) the parallel or serial microprocessor interface - access of on-chip registers via p interface address/data format - activation/deactivation control of u- and s-transceiver via p interface and c/i handler - t-smint i is monitor channel master - tic bus is transparent on iom ?2 interface and is used for d-channel arbitration between s-transceiver and off-chip hdlc controllers. s u u - interface s/t - interface idcc peb2023 slicofi - 2 hv - slic hv - slic iom-2 p pots interface iom-2 4x hdlc c 165 core usb/ v.24 utah usb / v.24 interface hentappl.vsd t-sminti pef82902 dc/dc converter pef 82902 overview data sheet 14 2001-11-09 figure 4 control via p interface alternatively, the t-smint i can be controlled via b) the iom -2 interface - access of on-chip registers via the monitor channel with header/address/data format (device is monitor slave) - activation/deactivation control of u- and s-transceiver via the c/i channels ci0 and ci1 - tic bus is transparent on iom ?2 interface and is used for d-channel arbitration between s-transceiver and off-chip hdlc controllers. s u c - interface iom -2 iom-2 slave e.g. slicofi-2 c mon c/i register mon c/i1 c/i0 iommaster.vsd pef 82902 overview data sheet 15 2001-11-09 figure 5 control via iom -2 interface s u iom -2 iom-2 master e.g. utah register c/i1 c/i0 mon iomslave.vsd int pef 82902 functional description data sheet 16 2001-11-09 2 functional description 2.1 microcontroller interfaces the t-smint i supports either a serial or a parallel microcontroller interface. for applications where no controller is connected to the t-smint i microcontroller interface, register programming is done via the iom -2 monitor channel from a master device. in such applications the t-smint i operates in the iom -2 slave mode (refer to the corresponding chapter of the iom -2 monitor handler). the interface selections are all done by pinstrapping. the possible interface selections are listed in table 4 . the selection pins are evaluated when the reset input rst is released. for the pin levels stated in the tables the following is defined: ? high ? :dynamic pin value which must be ? high ? when the pin level is evaluated v dd , v ss :static ? high ? or ? low ? level (tied to v dd , v ss ) note: for a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to v dd . the microcontroller interface also consists of a microcontroller clock generation at pin mclk, an interrupt request at pin int , a reset input pin rst and a reset output pin rsto . the interrupt request pin int (open drain output) becomes active if the t-smint i requests an interrupt. 2.1.1 serial control interface (sci) the serial control interface (sci) is compatible to the spi interface of motorola and to the siemens c510 family of microcontrollers. the sci consists of 4 lines: sclk, sdx, sdr and cs . data is transferred via the lines sdr and sdx at the rate given by sclk. the falling edge of cs indicates the beginning table 4 interface selection for the t-smint i pins serial /parallel interface pins interface type/mode wr (r/w) rd (ds) cs ale v dd motorola ? high ?? high ? parallel ? high ? v ss siemens/intel non-mux edge siemens/intel mux v ss v ss serial ? high ? v ss serial control interface(sci) v ss v ss iom -2 monitor channel (slave mode) pef 82902 functional description data sheet 17 2001-11-09 of a serial access to the registers. the t-smint i latches incoming data at the rising edge of sclk and shifts out at the falling edge of sclk. each access must be terminated by a rising edge of cs . data is transferred in groups of 8 bits with the msb first. pad mode of sdx can be selected ? open drain ? or ? push-pull ? by programming mode2.ppsdx. figure 6 shows the timing of a one byte read/write access via the serial control interface. pef 82902 functional description data sheet 18 2001-11-09 figure 6 serial control interface timing cs sclk sdr sdx cs sclk sdr sdx sci_tim.vsd write access header command/address data 77 0 1 2 3 4 5 61 2 3 4 5 65 6 7 02 3 40 1 `0` write read access header command/address data 77 0 1 2 3 4 5 61 2 3 4 5 6 5 6 7 0 2 3 40 1 `1` read pef 82902 functional description data sheet 19 2001-11-09 2.1.1.1 programming sequences the basic structure of a read/write access to the t-smint i registers via the serial control interface is shown in figure 7 . figure 7 serial command structure a new programming sequence starts with the transfer of a header byte. the header byte specifies different programming sequences allowing a flexible and optimized access to the individual functional blocks of the t-smint i. the possible sequences are listed in table 5 and are described after that. header 40 h : non-interleaved a-d-a-d sequences the non-interleaved a-d-a-d sequences give direct read/write access to the address range 00 h -7f h and can have any length. in this mode sdx and sdr can be connected table 5 header byte code header byte sequence sequence type access to 40 h adr-data-adr-data non-interleaved address range 00 h -7f h 48 h interleaved 43 h adr-data-data-data read-/write-only address range 00 h -7f h 41 h non-interleaved 49 h interleaved sdr write sequence: read sequence: sdr 7 076 07 0 write data address (command) read data 0 1 write read 7 076 07 0 header byte 2 byte 3 header byte 2 byte 3 sdx address (command) pef 82902 functional description data sheet 20 2001-11-09 together allowing data transmission on one line. example for a read/write access with header 40 h : header 48 h : interleaved a-d-a-d sequences the interleaved a-d-a-d sequences give direct read/write access to the address range 00 h -7f h and can have any length. this mode allows a time optimized access to the registers by interleaving the data on sdx and sdr. example for a read/write access with header 48 h : header 43 h : read-/write- only a-d-d-d sequence generally, it can be used for any register access to the address range 20 h -7d h . the sequence can have any length and is terminated by the rising edge of cs . example for a write access with header 43 h : example for a read access with header 43 h : header 41 h : non-interleaved a-d-d-d sequence this sequence (header 41 h ) allows in front of the a-d-d-d write access a non- interleaved a-d-a-d read access. generally, it can be used for any register access to the address range 20 h -7d h .the termination condition of the read access is the reception of the wradr. the sequence can have any length and is terminated by the rising edge of cs . sdr header wradr wrdata rdadr rdadr wradr wrdata sdx rddata rddata sdr header wradr wrdata rdadr rdadr wradr wrdata sdx rddata rddata sdr header wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx sdr header rdadr sdx rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) rddata (rdadr) pef 82902 functional description data sheet 21 2001-11-09 example for a read/write access with header 41 h : header 49 h : interleaved a-d-d-d sequence this sequence (header 49 h ) allows in front of the a-d-d-d write access an interleaved a-d-a-d read access. generally, it can be used for any register access to the address range 20 h -7d h .the termination condition of the read access is the reception of the wradr. the sequence can have any length and is terminated by the rising edge of cs . example for a read/write access with header 49 h : 2.1.2 parallel microcontroller interface the 8-bit parallel microcontroller interface with address decoding on chip allows an easy and fast microcontroller access. the parallel interface of the t-smint i provides three types of p busses which are selected via pin ale. the bus operation modes with corresponding control pins are listed in table 6 . the occurrence of an edge on ale, either positive or negative, at any time during the operation immediately selects the interface type (3). a return to one of the other interface types is possible only if a hardware reset is issued. note: for a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied to v dd . a read/write access to the t-smint i registers can be done in multiplexed or non- multiplexed mode. in non-multiplexed mode the register address must be applied to the address bus (a0- a6) for the data access via the data bus (d0-d7). sdr header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx rddata rddata sdr header rdadr rdadr wradr wrdata (wradr) wrdata (wradr) wrdata (wradr) sdx rddata rddata table 6 bus operation modes bus mode pin ale control pins (1) motorola v dd cs , r/w , ds (2) siemens/intel non-multiplexed v ss cs , wr , rd (3) siemens/intel multiplexed edge cs , wr , rd , ale pef 82902 functional description data sheet 22 2001-11-09 in multiplexed mode the address on the address bus (ad0-ad7) is latched in by ale before a read/write access via the address/data bus is performed. the t-smint i provides two different ways to address the register contents which can be selected with the amod bit in the mode2 register. the address mode after reset is the indirect address mode (amod = ? 0 ? ). reprogramming into the direct address mode (amod = ? 1 ? ) has to take place in the indirect address mode. figure 8 illustrates both register addressing modes. direct address mode (amod = ? 1 ? ): the register address to be read or written is directly set in the way described above. indirect address mode (amod = ? 0 ? ): non-muxed: only the lsb of the address bus (a0) muxed: only the lsb of the address-data bus (ad0) gets evaluated to address a virtual address (0 h ) and a virtual data (1 h ) register. every access to a target register consists of: a write access (muxed or non-muxed) to address to store the target register s address, as well as a read access (muxed or non-muxed) from data to read from the target register or a write access (muxed or non-muxed) to data to write to the target register figure 8 direct/indirect register address mode data a0 address 1h 0h data data a6 - a0 00h 01h 02h 03h 04h 7ch 7dh 7eh 7fh d7 - d0 d7 - d0 indirect address mode amod = 0 (default) direct address mode amod = 1 regacces.vsd pef 82902 functional description data sheet 23 2001-11-09 2.1.3 microcontroller clock generation the microcontroller clock is derived from the unregulated 15.36 mhz clock from the oscillator and provided by the pin mclk. five clock rates are selectable by a programmable prescaler which is controlled by the bits mode1.mclk and mode1.cds corresponding to the following table. table 7 mclk frequencies the clock rate is changed after cs becomes inactive. 2.2 reset generation figure 9 shows the organization of the reset generation of the t-smint i. mode1. mclk bits mclk frequency with mode1.cds = ?0? mclk frequency with mode1.cds = ?1? 0 0 3.84 mhz 7.68 mhz 0 1 0.96 mhz 1.92 mhz 1 0 7.68 mhz 15.36 mhz 1 1 disabled disabled pef 82902 functional description data sheet 24 2001-11-09 . figure 9 reset generation of the t-smint i 1) reset source selection the internal reset sources c/i code change and watchdog timer can be output at the low active reset pin rsto . these reset sources can be selected with the rss2,1 bits in the mode1 register according to table 8 . 1) the ? or ? -gates shall illustrate in a symbolic way, that ? source a active ? or ? source b active ? is forwarded. the real polarity of the different sources is not considered. watchdog c/i0 code change (exchange awake) software reset register (sres) reset functional block res_ci res_s res_hdlc res_u internal reset of all registers 1 1 por/uvd vdddet rst pin rss2,1 rss2,1 rss1 resetgen.vsd rsto 0,1= open 0 1 1,x 0,0 125s t 250s t = 125s deacti- vation delay vdddet 0 1 reset mode1 register 0 1 pef 82902 functional description data sheet 25 2001-11-09 the internal reset sources set the mode1 register to its reset value. table 8 reset source selection c/i code change (exchange awake) a change in the downstream c/i channel (c/i0) generates a reset pulse of 125 s t 250 s. watchdog timer after the selection of the watchdog timer (rss = ? 11 ? ) an internal timer is reset and started. during every time period of 128 ms the microcontroller has to program the wtc1- and wtc2 bits in the following sequence to reset and restart the watchdog timer: otherwise the timer expires and a wov-interrupt (ista register) together with a reset out pulse on pin rsto of 125 s is generated. deactivation of the watchdog timer is only possible with a hardware reset (including expiration of the watchdog timer). as in the scout-s, the watchdog timer is clocked with the iom -2 clocks and works only if the internal iom -2 clocks are active. hence, the power consumption is minimized in state power down. software reset register (sres) several main functional blocks of the t-smint i can be reset separately by software setting the corresponding bit in the sres register. this is equivalent to a hardware reset of the corresponding functional block. the reset state is activated as long as the bit is set to ? 1 ? . rss2 bit 1 rss1 bit 0 c/i code change watchdog timer por/uvd 1) and rst 1) por/uvd can be enabled/disabled via pin vdddet 00 -- -- x 0 1 /rsto disabled (= high impedance) 10 x -- x 11 -- x x wtc1 wtc2 1. 2. 1 0 0 1 pef 82902 functional description data sheet 26 2001-11-09 external reset input at the rst input an external reset can be applied forcing the t-smint i in the reset state. this external reset signal is additionally fed to the rsto output. after release of an external reset, the c has to wait for min. t c before it starts read or write access to the t-smint i (see table 37 ). reset ouput if vdddet is active, then the deactivation of a reset output on rsto is delayed by t deact (see table 38 ). reset generation the t-smint i has an on-chip reset generator based on a power-on reset (por) and under voltage detection (uvd) circuit (see table 38 ). the por/uvd requires no external components. the por/uvd circuit can be disabled via pin vdddet . the requirements on v dd ramp-up during power-on reset are described in chapter 5.6.5 . clocks and data lines during reset during reset the data clock (dcl), the bit clock (bcl), the microcontroller clock 1) (mclk) and the frame synchronization (fsc) keep running. during reset dd and du are high; with the exception of: the output c/i code from the u-transceiver on dd iom -2 channel 0 is ? dr ? = 0000 (value after reset of register ucir = ? 00 h ? ) the output c/i code from the s-transceiver on du iom -2 channel 1 is ? tim ? = 0000. 1) during a power-on/uvd reset, the microcontroller clock mclk is not running, but starts running as soon as timer t deac is started. pef 82902 functional description data sheet 27 2001-11-09 2.3 iom ? -2 interface the t-smint i supports the iom -2 interface in terminal mode (dcl=1.536 mhz) according to the iom -2 reference guide [12]. 2.3.1 iom -2 functional description the iom -2 interface consists of four lines: fsc, dcl, dd, du and optionally bcl. the rising edge of fsc indicates the start of an iom -2 frame. the dcl and the bcl clock signals synchronize the data transfer on both data lines du and dd. the dcl is twice the bit rate, the bcl rate is equal to the bit rate. the bits are shifted out with the rising edge of the first dcl clock cycle and sampled at the falling edge of the second clock cycle. with bcl the bits are shifted out with the rising edge and sampled with the falling edge of the single clock cycle. the iom -2 interface can be enabled/disabled with the dis_iom bit in the iom_cr registerthe fsc signal is an 8 khz frame sync signal. the number of pcm timeslots on the receive and transmit lines is determined by the frequency of the dcl clock (or bcl), with the 1.536 mhz (bcl=768 khz) clock 3 channels consisting of 4 timeslots each are available. iom ? -2 frame structure of the t-smint i the frame structure on the iom -2 data ports (du,dd) of the t-smint i with a dcl clock of 1.536 mhz (or bcl=768 khz) and if tic bus is not disabled (iom_cr.tic_dis) is shown in figure 10 . figure 10 iom ? -2 frame structure of the t-smint i macro_19 pef 82902 functional description data sheet 28 2001-11-09 the frame is composed of three channels: channel 0 contains 144-kbit/s of user and signaling data (2b + d), a monitor programming channel (mon0) and a command/indication channel (ci0) for control and programming of e.g. the u-transceiver. channel 1 contains two 64-kbit/s intercommunication channels (ic), a monitor programming channel (mon1) and a command/indication channel (ci1) for control and programming of e.g. the s-transceiver. channel 2 is used for d-channel access mechanism (tlc-bus, s/g bit). additionally, channel 2 supports further ic and mon channels. 2.3.2 iom -2 handler the iom -2 handler offers a great flexibility for handling the data transfer between the different functional units of the t-smint i and voice/data devices connected to the iom -2 interface. additionally it provides a microcontroller access to all time slots of the iom -2 interface via the four controller data access registers (cda). the pcm data of the functional units s-transceiver (s) and the controller data access (cda) can be configured by programming the time slot and data port selection registers (tsdp). with the tss bits (time slot selection) the pcm data of the functional units can be assigned to each of the 12 pcm time slots of the iom -2 frame. with the dps bit (data port selection) the output of each functional unit is assigned to du or dd respectively. the input is assigned vice versa. with the control registers (cr) the access to the data of the functional units can be controlled by setting the corresponding control bits (en, swap). the iom -2 handler also provides access to the u and s transceiver monitor channel c/i channels (ci0,ci1) tic bus (tic) the access to these channels is controlled by the registers s_cr, ci_cr and mon_cr. the iom -2 interface with the two serial data strobes (sds1,2) is controlled by the control registers iom_cr, sds1_cr and sds2_cr. the following figure 11 shows the architecture of the iom -2 handler. pef 82902 functional description data sheet 29 2001-11-09 figure 11 architecture of the iom -2 handler ci_cr 21150_0 7 control data access (tsdp, dps, en, swap, tbm, mcda, sti) cda registers cda10 cda11 cda20 cda21 cda_tsdpxy cda_crx mcda sti msti asti controller data access (cda) control monitor data mon_cr tic bus disable iom_cr control c/i1 data control transceiver data access (tss, dps, en) s_tsdp_b1 s_tsdp_b2 s_cr d/b1/b2 data c/i0 data c/i1 data c/i0 data tic bus data monitor data cda data transceiver data (tr=u/s) tr_b1_x tr_b2_x tr_d_x tr_b1_r tr_b2_r tr_d_r mon handler tic c/i0 c/i1 data microcontroller interface sds1/2_cr iom_cr (en, tlen, tss) iom-2 interface (en, od) du dd fsc dcl bcl/sclk sds1 sds2 iom-2 handler tr represents the u and s transceiver pef 82902 functional description data sheet 30 2001-11-09 2.3.2.1 controller data access (cda) the four controller data access registers (cda10, cda11, cda20, cda21) provide microcontroller access to the 12 iom -2 time slots and more: looping of up to four independent pcm channels from du to dd or vice versa over the four cda registers shifting or switching of two independent pcm channels to another two independent pcm channels on both data ports (du, dd). between reading and writing the data can be manipulated (processed with an algorithm) by the microcontroller. if this is not the case a switching function is performed. monitoring of up to four time slots on the iom -2 interface simultaneously microcontroller read and write access to each pcm channel the access principle, which is identical for the two channel register pairs cda10/11 and cda20/21, is illustrated in figure 12 . the index variables x,y used in the following description can be 1 or 2 for x, and 0 or 1 for y. the prefix ? cda_ ? from the register names has been omitted for simplification. to each of the four cdaxy data registers a tsdpxy register is assigned by which the time slot and the data port can be determined. with the tss (time slot selection) bits a time slot from 0...11 can be selected. with the dps (data port selection) bit the output of the cdaxy register can be assigned to du or dd respectively. the time slot and data port for the output of cdaxy is always defined by its own tsdpxy register. the input of cdaxy depends on the swap bit in the control registers crx. if the swap bit = ? 0 ? (swap is disabled) the time slot and data port for the input and output of the cdaxy register is defined by its own tsdpxy register. if the swap bit = ? 1 ? (swap is enabled) the input port and time slot of the cdax0 is defined by the tsdp register of cdax1 and the input port and time slot of cdax1 is defined by the tsdp register of cdax0. the input definition for time slot and data port cdax0 are thus swapped to cdax1 and for cdax1 swapped to cdax0. the output timeslots are not affected by swap. the input and output of every cdaxy register can be enabled or disabled by setting the corresponding en (-able) bit in the control register cdax_cr. if the input of a register is disabled the output value in the register is retained. usually one input and one output of a functional unit (transceiver, cda register) is programmed to a timeslot on iom -2 (e.g. for b-channel transmission in upstream direction the s-transceiver writes data onto iom -2 and the u-transceiver reads data from iom -2). for monitoring data in such cases a cda register is programmed as described below under ? monitoring data ? . besides that none of the iom -2 timeslots must be assigned more than one input and output of any functional unit. pef 82902 functional description data sheet 31 2001-11-09 . figure 12 data access via cdax0 and cdax1 register pairs looping and shifting data figure 13 gives examples for typical configurations with the above explained control and configuration possibilities with the bits tss, dps, en and swap in the registers tsdpxy or cdax_cr: a) looping iom -2 time slot data from du to dd or vice versa (swap = ? 0 ? ) b) shifting data from tsa to tsb and tsc to tsd in both transmission directions (swap = ? 1 ? ) c) switching data from tsa to tsb and looping from du to dd or switching tsc to tsd and looping from dd to du . tsa is programmed in tsdp10, tsb in tsdp11, tsc in tsdp20 and tsd in tsdp21. x = 1 or 2; a,b = 0...11 iom_hand.fm4 du cdax1 control register cda_crx dd 1 1 time slot selection (tss) 1 data port cda_tsdpx1 0 1 0 1 1 0 1 1 enable input (en_o0) output cda_tsdpx0 1 0 cdax0 1 (en_i0) (en_i1) input enable output (en_o1) selection (dps) data port selection (dps) selection (tss) time slot tsa tsa tsb tsb input swap (swap) pef 82902 functional description data sheet 32 2001-11-09 figure 13 examples for data access via cdaxy registers a) looping data b) shifting (switching) data c) switching and looping data tsa tsb tsc tsd cda10 cda11 cda20 cda21 tsa tsb tsc tsd du dd tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd b) shifting data a) looping data .tss: .dps .swap ? 0 ? ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 0 ? tsa tsb tsc tsd .tss: .dps .swap ? 1 ? ? 1 ? ? 0 ? ? 1 ? ? 0 ? ? 1 ? tsa tsb tsc tsd cda10 cda11 cda20 cda21 du dd c) switching data tsa tsb tsc tsd .tss: .dps .swap ? 1 ? ? 1 ? ? 1 ? ? 0 ? ? 0 ? ? 1 ? pef 82902 functional description data sheet 33 2001-11-09 figure 14 shows the timing of looping tsa from du to dd via cdaxy register. tsa is read in the cdaxy register from du and is written one frame later on dd. figure 15 shows the timing of shifting data from tsa to tsb on du(dd). in figure 15 a) shifting is done in one frame because tsa and tsb didn ? t succeed directly one another (a = 0...9 and b a+2) . in figure 15 b) shifting is done from one frame to the following frame. this is the case when the time slots succeed one other (b = a+1) or b is smaller than a (b < a). at looping and shifting the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the status overflow interrupt (stov). sti and stov are explained in the section ? synchronous transfer ? . if there is no controller intervention the looping and shifting is done autonomously. . figure 14 data access when looping tsa from du to dd tsa du tsa fsc cdaxy c rd wr ack stov tsa dd tsa sti *) if access by the c is required *) pef 82902 functional description data sheet 34 2001-11-09 figure 15 data access when shifting tsa to tsb on du (dd) tsa du tsb fsc cdaxy c rd wr ack stov sti tsa sti tsa fsc cdaxy c rd wr ack stov sti tsb tsa tsb (dd) (a,b: 0...11 and (b = a+1 or b pef 82902 functional description data sheet 36 2001-11-09 or 88 h for monitoring from dd. by this it is possible to monitor the tic bus (ts11) and the odd numbered d-channel (ts3) simultaneously on du and dd. synchronous transfer while looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (sti) and the synchronous transfer overflow interrupt (stov). the microcontroller access to each of the cdaxy registers can be synchronized by means of four programmable synchronous transfer interrupts (stixy) 1) and synchronous transfer overflow interrupts (stovxy) 2) in the sti register. depending on the dps bit in the corresponding tsdpxy register the stixy is generated two (for dps= ? 0 ? ) or one (for dps= ? 1 ? ) bcl clock after the selected time slot (cda_tsdpxy.tss). one bcl clock is equivalent to two dcl clocks. in the following description the index xy 0 and xy 1 are used to refer to two different interrupt pairs (sti/stov) out of the four cda interrupt pairs (sti10/stov10, sti11/ stov11, sti20/stov20, sti21/stov21). a stovxy 0 is related to its stixy 0 and is only generated if stixy 0 is enabled and not acknowledged. however, if stixy 0 is masked, the stovxy0 is generated for any other stixy1 which is enabled and not acknowledged. table 9 gives some examples for that. it is assumed that a stov interrupt is only generated because a sti interrupt was not acknowledged before. in example 1 only the stixy 0 is enabled and thus stixy 0 is only generated. if no sti is enabled, no interrupt will be generated even if stov is enabled (example 2). in example 3 stixy 0 is enabled and generated and the corresponding stovxy 0 is disabled. stixy 1 is disabled but its stovxy 1 is enabled, and therefore stovxy 1 is generated due to stixy 0 . in example 4 additionally the corresponding stovxy 0 is enabled, so stovxy 0 and stovxy 1 are both generated due to stixy 0 . in example 5 additionally the stixy 1 is enabled with the result that stovxy 0 is only generated due to stixy 0 and stovxy 1 is only generated due to stixy 1 . compared to the previous example stovxy 0 is disabled in example 6, so stovxy 0 is not generated and stovxy 1 is only generated for stixy 1 but not for stixy 0 . 1) in order to enable the sti interrupts the input of the corresponding cda register has to be enabled. this is also valid if only a synchronous write access is wanted. the enabling of the output alone does not effect an sti interrupt. 2) in order to enable the stov interrupts the output of the corresponding cda register has to be enabled. this is also valid if only a synchronous read access is wanted. the enabling of the input alone does not effect an interrupt. pef 82902 functional description data sheet 37 2001-11-09 compared to example 5 in example 7 a third stovxy 2 is enabled and thus stovxy2 is generated additionally for both stixy 0 and stixy 1 . a stov interrupt is not generated if all stimulating sti interrupts are acknowledged. a stixy must be acknowledged by setting the ackxy bit in the asti register two bcl clock (for dps= ? 0 ? ) or one bcl clocks (for dps= ? 1 ? ) before the time slot which is selected for the appropriate stixy. the interrupt structure of the synchronous transfer is shown in figure 17 . table 9 examples for synchronous transfer interrupts enabled interrupts (register msti) generated interrupts (register sti) sti stov sti stov xy 0 -xy 0 -example 1 -xy 0 - - example 2 xy 0 xy 1 xy 0 xy 1 example 3 xy 0 xy 0 ; xy 1 xy 0 xy 0 ; xy 1 example 4 xy 0 ; xy 1 xy 0 ; xy 1 xy 0 xy 1 xy 0 xy 1 example 5 xy 0 ; xy 1 xy 1 xy 0 xy 1 - xy 1 example 6 xy 0 ; xy 1 xy 0 ; xy 1 ; xy 2 xy 0 xy 1 xy 0 ; xy 2 xy 1 ; xy 2 example 7 pef 82902 functional description data sheet 38 2001-11-09 . figure 17 interrupt structure of the synchronous data transfer figure 18 shows some examples based on the timeslot structure. figure a) shows at which point in time a sti and stov interrupt is generated for a specific timeslot. figure b) is identical to example 3 above, figure c) corresponds to example 5 and figure d) shows example 4. cic st mos s wov cic st mos s wov int sti11 ista mask msti sti sti10 sti20 sti21 stov10 stov11 stov20 stov21 sti11 sti10 sti20 sti21 stov10 stov11 stov20 stov21 ack11 asti ack10 ack20 ack21 u u 1 0 1 0 pef 82902 functional description data sheet 39 2001-11-09 . figure 18 examples for the synchronous transfer interrupt control with one stixy enabled . xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '1' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 a) interrupts for data access to time slot 0 (b1 after reset), msti.sti10 and msti.stov10 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '1' '1' '1' '0' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 b) interrupts for data access to time slot 0 (b1 after reset), stov interrupt used as flag for "last possible cda access"; msti.sti10 and msti.stov20 enabled c) interrupts for data access to time slot 0 and 1 (b1 and b2 after reset), msti.sti10, msti.stov10, msti.sti11 and msti.stov11 enabled sti_stov.vsd xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '0' '1' '1' msti.stovxy: '0' '0' '1' '1' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 d) interrupts for data access to time slot 0 (b1 after reset), stov20 interrupt used as flag for "last possible cda access", stov10 interrupt used as flag for "cda access failed"; msti.sti10, msti.stov10 and msti.stov20 enabled xy: 10 11 21 20 cda_tdspxy.tss: ts0 ts1 ts5 ts11 msti.stixy: '0' '1' '1' '1' msti.stovxy: '0' '1' '1' '0' ts7 ts5 ts6 ts4 ts3 ts1 ts2 ts0 ts11 ts9 ts10 ts8 ts0 ts11 : stov interrupt generated for a not acknowledged sti interrupt : sti interrupt generated pef 82902 functional description data sheet 40 2001-11-09 2.3.2.2 serial data strobe signal for time slot oriented standard devices at the iom -2 interface, the t-smint i provides two independent data strobe signals sds1 and sds2. the two strobe signals can be generated with every 8-khz-frame and are controlled by the registers sds1/2_cr. by programming the tss bits and three enable bits (ens_tss, ens_tss+1, ens_tss+3) a data strobe can be generated for the iom -2 time slots ts, ts+1 and ts+3 (bit7,6) and the combinations of them. the data strobes for ts and ts+1 are always 8 bits long (bit7 to bit0) whereas the data strobe for ts+3 is always 2 bits long (bit7, bit6). figure 19 data strobe signal generation fsc dd,du m r m x d ci0 sds1,2 (example1) sds1,2 (example2) sds1,2 (example3) tss ens_tss ens_tss+1 ens_tss+3 example 1: = '0 h ' = '0' = '1' = '0' tss ens_tss ens_tss+1 ens_tss+3 example 2: = '5 h ' = '1' = '1' = '0' tss ens_tss ens_tss+1 ens_tss+3 example 3: = '0 h ' = '1' = '1' = '1' ts0 ts11 ts10 ts9 ts8 ts7 ts6 ts5 ts4 ts3 ts2 ts1 ts0 ts1 b1 b2 mon0 ic1 ic2 mon1 m r m x ci1 strobe.vsd pef 82902 functional description data sheet 41 2001-11-09 figure 19 shows three examples for the generation of a strobe signal. in example 1 the sds is active during channel b2 on iom -2, whereas in the second example during ic2 and mon1. the third example shows a strobe signal for 2b+d channels which is used e.g. at an idsl (144 kbit/s) transmission. 2.3.3 iom -2 monitor channel the iom -2 monitor channel is utilized for information exchange between the t- smint i and other devices in the monitor channel. the montior channel data can be controlled by the bits in the monitor control register (mon_cr). for the transmission of the monitor data one of the 3 iom -2 channels can be selected by setting the monitor channel selection bits (mcs) in the monitor control register (mon_cr). the dps bit in the same register selects between an output on du or dd respectively and with en_mon the monitor data can be enabled/disabled. the default value is monitor channel 0 (mon0) enabled and transmission on dd. the monitor channel of the t-smint i can be used in the following applications (refer also to and ): as a master device the t-smint i can program and control other devices (e.g. psb 2161) attached to the iom -2, which therefore, do not need a microcontroller interface. as a slave device the t-smint i is programmed and controlled from a master device on iom -2 (e.g. utah). this is used in applications where no microcontroller is connected directly to the t-smint i. the monitor channel operates according to the iom -2 reference guide [12]. note: in contrast to the ntc-t, the t-smint i does neither issue nor react on monitor commands (mon0,1,2,8). instead, the t-smint i operated in iom -2 slave mode must be programmed via new monitor channel concept (see chapter 2.3.3.4 ), which provides full register access. the monitor time out procedure is available. reporting of the t-smint i is performed via interrupts. 2.3.3.1 handshake procedure the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure using the monitor channel receive (mr) and monitor channel transmit (mx) bits. data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted once per 8-khz frame until the transfer is acknowledged via the mr bit. pef 82902 functional description data sheet 42 2001-11-09 the monitor channel protocol is described in the following section and figure 22 shall illustrate this. the relevant control and status bits for transmission and reception are listed in table 10 and table 11 . table 10 transmit direction control/ status bit register bit function control mocr mxc mx bit control mie transmit interrupt (mda, mab, mer) enable status mosr mda data acknowledged mab data abort msta mac transmission active table 11 receive direction control/ status bit register bit function control mocr mrc mr bit control mre receive interrupt (mdr) enable status mosr mdr data received mer end of reception pef 82902 functional description data sheet 43 2001-11-09 figure 20 monitor channel protocol (iom ? -2) before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. this is indicated by a ? 0 ? in the monitor channel active mac status bit. after having written the monitor data transmit (mox) register, the microprocessor sets the monitor transmit control bit mxc to ? 1 ? . this enables the mx bit to go active (0), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. as a result, the receiving device stores the monitor byte in its monitor receive mor register and generates a mdr interrupt status. alerted by the mdr interrupt, the microprocessor reads the monitor receive (mor) register. when it is ready to accept data (e.g. based on the value in mor, which in a point-to-multipoint application might be the address of the destination device), it sets the mr control bit mrc to ? 1 ? to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. in addition, itd10032 mon mx transmitter mr 1 1 ff ff 1 1 adr 0 1 0 0 data1 0 1 data1 adr 0 0 data1 0 1 data1 0 0 0 0 data2 0 1 data2 data2 0 1 data2 0 0 ff 1 0 ff 1 0 ff 1 1 ff 1 1 receiver mie = 1 mox = adr mxc = 1 mac = 1 mox = data1 mda int. mda int. mda int. mxc = 0 mdr int. rd mor (=adr) mrc = 1 mdr int. mdr int. mrc = 0 mer int. p p 125 s rd mor (=data1) rd mor (=data2) mox = data2 mac = 0 pef 82902 functional description data sheet 44 2001-11-09 it enables other monitor channel interrupts by setting monitor interrupt enable (mie) to ? 1 ? . as a result, the first monitor byte is acknowledged by the receiving device setting the mr bit to ? 0 ? . this causes a monitor data acknowledge mda interrupt status at the transmitter. a new monitor data byte can now be written by the microprocessor in mox. the mx bit is still in the active (0) state. the transmitter indicates a new byte in the monitor channel by returning the mx bit active after sending it once in the inactive state. as a result, the receiver stores the monitor byte in mor and generates a new mdr interrupt status. when the microprocessor has read the mor register, the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate a mda interrupt status. this "mda interrupt ? write data ? mdr interrupt ? read data ? mda interrupt" handshake is repeated as long as the transmitter has data to send. note that the monitor channel protocol imposes no maximum reaction times to the microprocessor. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor transmit control bit mxc to ? 0 ? . this enforces an inactive ( ? 1 ? ) state in the mx bit. two frames of mx inactive signifies the end of a message. thus, a monitor channel end of reception mer interrupt status is generated by the receiver when the mx bit is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mr control bit mrc to 0, which in turn enforces an inactive state in the mr bit. this marks the end of the transmission, making the monitor channel active mac bit return to ? 0 ? . during a transmission process, it is possible for the receiver to ask a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mr control bit mrc to ? 0 ? . an aborted transmission is indicated by a monitor channel data abort mab interrupt status at the transmitter. the monitor transfer protocol rules are summarized in the following section a pair of mx and mr in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission . a start of a transmission is initiated by the transmitter by setting the mxc bit to ? 1 ? enabling the internal mx control. the receiver acknowledges the received first byte by setting the mr control bit to ? 1 ? enabling the internal mr control. the internal mx, mr control indicates or acknowledges a new byte in the mon slot by toggling mx, mr from the active to the inactive state for one frame. two frames with the mr-bit set to inactive indicate a receiver request for abort . the transmitter can delay a transmission sequence by sending the same byte continuously. in that case the mx-bit remains active in the iom -2 frame following the first byte occurrence. delaying a transmission sequence is only possible while the receiver mr-bit and the transmitter mx-bit are active. pef 82902 functional description data sheet 45 2001-11-09 since a double last-look criterion is implemented the receiver is able to receive the mon slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two successive frames. to control this handshake procedure a collision detection mechanism is implemented in the transmitter. this is done by making a collision check per bit on the transmitted monitor data and the mx bit. monitor data will be transmitted repeatedly until its reception is acknowledged or the transmission time-out timer expires. two frames with the mx bit in the inactive state indicates the end of a message (eom). transmission and reception of monitor messages can be performed simultaneously. this feature is used by the device to send back the response before the transmission from the controller is completed (the device does not wait for eom from controller). 2.3.3.2 error treatment in case the device does not detect identical monitor messages in two successive frames, transmission is not aborted. instead the device will wait until two identical bytes are received in succession. a transmission is aborted by the device if an error in the mr handshaking occurs a collision on the iom -2 bus of the monitor data or mx bit occurs the transmission time-out timer expires a reception is aborted by the device if an error in the mx handshaking occurs or an abort request from the opposite device occurs mx/mr treatment in error case in the master mode the mx/mr bits are under control of the microcontroller through mxc or mrc, respectively. an abort is indicated by an mab interrupt or mer interrupt, respectively. in the slave mode the mx/mr bits are under control of the device. an abort is always indicated by setting the mx/mr bit inactive for two or more iom -2 frames. the controller must react with eom. figure 21 shows an example for an abort requested by the receiver, figure 22 shows an example for an abort requested by the transmitter and figure 23 shows an example for a successful transmission. pef 82902 functional description data sheet 46 2001-11-09 figure 21 monitor channel, transmission abort requested by the receiver figure 22 monitor channel, transmission abort requested by the transmitter figure 23 monitor channel, normal end of transmission mx (du) iom -2 frame no. 1 2 345 67 eom mr (dd) 1 0 1 0 mon_rec-abort.vsd abort request from receiver mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_tx-abort.vsd abort request from transmitter mr (du) iom -2 frame no. 1 2 345 67 mx (dd) 1 0 1 0 eom mon_norm.vsd 8 pef 82902 functional description data sheet 47 2001-11-09 2.3.3.3 monitor channel programming as a master device the master mode is selected by default if one of the microcontroller interfaces is selected. the monitor data is written by the microcontroller in the mox register and transmitted via iom -2 dd(du) line to the programmed/controlled device e.g. arcofi- ba psb 2161. the transfer of the commands in the mon channel is regulated by the handshake protocol mechanism with mx, mr. 2.3.3.4 monitor channel programming as a slave device monitor slave mode can be selected by pinstrapping the microcontroller interface pins according to table 4 . all programming data required by the device is received in the monitor time slot on the iom -2 and is transferred to the mor register. the transfer of the commands in the mon channel is regulated by the handshake protocol mechanism with mx, mr which is described in the previous chapter 2.3.3.1 . the first byte of the monitor message must contain in the higher nibble the monitor channel address code which is ? 1000 ? for the t-smint i. the lower nibble distinguishes between a programming command and an identification command. identification command in order to be able to identify unambiguously different hardware designs of the t- smint i by software, the following identification command is used: the t-smint i responds to this identification sequence by sending a identification sequence: design: six bit code, specific for each device in order to identify differences in operation (see ?id - identification register? on page 139 ). this identification sequence is usually done once, when the t-smint i is connected for the first time. this function is used so that the software can distinguish between different possible hardware configurations. however this sequence is not compulsory. programming sequence the programming sequence is characterized by a ? 1 ? being sent in the lower nibble of the received address code. the data structure after this first byte is equivalent to the structure of the serial control interface described in chapter chapter 2.1.1 . du 1st byte value 10000000 du 2nd byte value 0 0 000000 dd 1st byte value 10000000 dd 2nd byte value 0 0 design pef 82902 functional description data sheet 48 2001-11-09 all registers can be read back when setting the r/w bit to ? 1 ? . the t-smint i responds by sending his iom -2 specific address byte (81 h ) followed by the requested data. note: application hint: it is not allowed to disable the mx- and mr-control in the programming device at the same time! first, the mx-control must be disabled, then the c has to wait for an end of reception before the mr-control may be disabled. otherwise, the t- smint i does not recognize an end of reception. 2.3.3.5 monitor time-out procedure to prevent lock-up situations in a monitor transmission a time-out procedure can be enabled by setting the time-out bit (tout) in the monitor configuration register (mconf). an internal timer is always started when the transmitter must wait for the reply of the addressed device or for transmit data from the microcontroller. after 40 iom -2 frames (5 ms) without reply the timer expires and the transmission will be aborted with an eom (end of message) command by setting the mx bit to ? 1 ? for two consecutive iom -2 frames. 2.3.3.6 monitor interrupt logic figure 24 shows the interrupt structure of the monitor handler. the monitor data receive interrupt status mdr has two enable bits, monitor receive interrupt enable (mre) and mr bit control (mrc). the monitor channel end of reception mer, monitor channel data acknowledged mda and monitor channel data abort mab interrupt status bits have a common enable bit monitor interrupt enable mie. mre set to ? 0 ? prevents the occurrence of mdr status, including when the first byte of a packet is received. when mre is set to ? 1 ? but mrc is set to ? 0 ? , the mdr interrupt status is generated only for the first byte of a receive packet. when both mre and mrc are set to ? 1 ? , mdr is always generated and all received monitor bytes - marked by a 1-to-0 transition in mx bit - are stored. additionally, a mrc set to ? 1 ? enables the control of the mr handshake bit according to the monitor channel protocol. du 1st byte value 1 0 0 0 0 0 0 1 du 2nd byte value header byte du 3rd byte value r/w command/ register address du 4th byte value data 1 du (nth + 3) byte value data n pef 82902 functional description data sheet 49 2001-11-09 figure 24 monitor interrupt structure 2.3.4 c/i channel handling the command/indication channel carries real-time status information between the t- smint i and another device connected to the iom -2. 1) c/i0 channel lies in iom -2 channel 0 and access may be arbitrated via the tic bus access protocol. in this case the arbitration is done in iom -2 channel 2. the c/i0 channel is accessed via register cir0 (received c/i0 data from dd) and register cix0 (transmitted c/i0 data to du). the c/i0 code is four bits long. in the receive direction, the code from layer-1 is continuously monitored, with an interrupt being generated any time a change occurs (ista.cic). c/i0 only: a new code must be found in two consecutive iom -2 frames to be considered valid and to trigger a c/i code change interrupt status (double last look criterion). in the transmit direction, the code written in cix0 is continuously transmitted in c/i0. 2) a second c/i channel (called c/i1) lies in iom -2 channel 1 and is used to convey real time status information of the on-chip s-transceiver or an external device. the c/i1 channel consists of four or six bits in each direction. the width can be changed from 4 bit to 6 bit by setting bit cix1.cicw. cic st mos s wov int ista cic st mos s wov u u mask mre mdr mie mda mer mab mosr mocr 0 1 1 0 pef 82902 functional description data sheet 50 2001-11-09 in 4-bit mode 6-bits are written whereby the higher 2 bits must be set to ? 1 ? and 6-bits are read whereby only the 4 lsbs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). the c/i1 channel is accessed via registers cir1 and cix1. the connection of cir1 and cix1 to dd and du, respectively, can be selected by setting bit ci_cr.dps_ci1. a change in the received c/i1 code is indicated by an interrupt status without double last look criterion. cic interrupt logic figure 25 shows the cic interrupt structure. the two corresponding status bits cic0 and cic1 are read in cir0 register. cic1 can be individually disabled by clearing the enable bit ci1e in the cix1 register. in this case the occurrence of a code change in cir1 will not be displayed by cic1 until the corresponding enable bit has been set to one. bits cic0 and cic1 are cleared by a read of cir0. an interrupt status is indicated every time a valid new code is loaded in cir0 or cir1. the cir0 is buffered with a fifo size of two. if a second code change occurs in the received c/i channel 0 before the first one has been read, immediately after reading of cir0 a new interrupt will be generated and the new code will be stored in cir0. if several consecutive codes are detected, only the first and the last code are obtained at the first and second register read, respectively. for cir1 no fifo is available. the actual code of the received c/i channel 1 is always stored in cir1. figure 25 cic interrupt structure cic st mos s wov int ista mask cic1 ci1e cic0 cir0 cix1 cic st mos s wov u u 0 1 0 1 pef 82902 functional description data sheet 51 2001-11-09 2.3.5 d-channel access control the upstream d-channel is arbitrated between the s-bus and external hdlc controllers via the tic bus (s/g, bac, tba bits) according to the iom -2 reference guide 1) . further to the implementation in the intc-q it is possible, to set the priority (8 or 10) of all hdlc-controllers connected to iom -2, which is particularly useful for use of the t- smint i together with the utah. 2.3.5.1 application examples for d-channel access control figure 26 and figure 27 show different scenarios for the local d-channel arbitration between the s-bus and the microcontroller. figure 26 d-channel arbitration: c with hdlc and direct access to tic bus 1) the a/b-bit is not supported by the u-transceiver hdlc hdlc hdlc hdlc s u p - i/f iom-2 i/f arbitr. e.g. utah; mpc860 iom-2 prio e-bit bac s/g d s/g bac d c has access to bac-bit and s/g-bit on iom-2. access to tba generally not required if only one local d-channel source. c t-smint i pef 82902 functional description data sheet 52 2001-11-09 figure 27 d-channel arbitration: c with hdlc and no access to tic bus 2.3.5.2 tic bus handling the tic bus is implemented to organize the access to the c/i0-channel and to the d- channel from up to 7 d-channels hdlc controllers. the arbitration mechanism must be activated by setting modeh.dim2-0=00x. the arbitration mechanism is implemented in the last octet in iom -2 channel 2 of the iom -2 interface (see figure 28 ). an access request to the tic bus may either be generated by software (c access to the c/i0-channel via cix0 register) or by an external d-channel hdlc controller (transmission of an hdlc frame in the d-channel). a software access request to the bus is effected by setting the bac bit in register cix0 to ? 1 ? (resulting in bac = ? 0 ? on iom -2). in the case of an access request by the t-smint i, the bus accessed-bit bac (bit 5 of last octet of ch2 on du, see figure 28 ) is checked for the status "bus free ? , which is indicated by a logical ? 1 ? . if the bus is free, the t-smint i transmits its individual tic bus address tad programmed in the cix0 register (cix0.tba2-0). while being transmitted the tic bus address tad is compared bit by bit with the value read back on du. if a sent bit set to ? 1 ? is read back as ? 0 ? because of the access of an external device with a lower tad, the t-smint i withdraws immediately from the tic bus, i.e. the remaining tad bits are not transmitted. the tic bus is occupied by the device which sends and reads back its address error-free. if more than one device attempt to seize the bus simultaneously, the one with the lowest address values wins. this one will set bac=0 on tic bus and starts d-channel transmission in the same frame. hdlc hdlc hdlc hdlc s u p - i/f iom-2 i/f arbitr. c e.g. mc68302 iom-2 prio e-bit bac s/g d s/g bac d cix0 cir0 . c/i channel handler c has access to bac, tba-bit and s/g-bit via tic-bus handler must poll s/g bit until s/g=0, then transmit d-channel c t-smint i pef 82902 functional description data sheet 53 2001-11-09 figure 28 structure of last octet of ch2 on du when the tic bus is seized by the t-smint i, the bus is identified to other devices as occupied via the du ch2 bus accessed-bit state ? 0 ? until the access request is withdrawn. after a successful bus access, the t-smint i is automatically set into a lower priority class, that is, a new bus access cannot be performed until the status "bus free" is indicated in two successive frames. if none of the devices connected to the iom -2 interface request access to the d and c/ i0 channels, the tic bus address 7 will be present. the device with this address will therefore have access, by default, to the d and c/i0 channels. note: bit bac (cix0 register) should be reset by the c when access is no more requested, to grant other devices access to the d and c/i0 channels. 2.3.5.3 stop/go bit handling the availability of the du d channel is indicated in bit 5 "stop/go" (s/g) of the last octet in dd channel 2 ( figure 29 ). the arbitration mechanism must be activated by setting modeh.dim2-0=0x1. s/g = 1 : stop s/g = 0 : go the stop/go bit is available to other layer-2 devices connected to the iom -2 interface to determine if they can access the d channel in upstream direction. b1 b2 mon0 d ci0 ic1 ic2 mon1 ci1 mx mr mx mr bac tad bus accessed ("1" no tic-bus access) itd02575.vsd bac tad 21 0 tic-bus address (tad 2 - 0) du pef 82902 functional description data sheet 54 2001-11-09 figure 29 structure of last octet of ch2 on dd 2.3.5.4 d-channel arbitration in intelligent nt applications (selected via register s_mode.mode2-0) the t-smint i has to share the upstream d-channel with one or more d-channel controllers on the iom -2 interface and with all connected tes on the s interface. the s-transceiver incorporates an elaborate state machine for d-channel priority handling on iom -2 ( chapter 2.3.5.5 ). for the access to the d-channel a similar arbitration mechanism as on the s interface (writing d-bits, reading back e-bits) is performed for all d-channel sources on iom -2. due to this an equal and fair access is guaranteed for all d-channel sources on both the s interface and the iom -2 interface. the access to the upstream d-channel is handled via the s/g bit for the hdlc controllers and via e-bit for all connected terminals on s (e-bits are inverted to block the terminals on s). furthermore, if more than one hdlc source is requesting d-channel access on iom -2 the tic bus mechanism is used (see chapter 2.3.5.2 ). the arbiter permanently counts the ? 1s ? in the upstream d-channel on iom -2. if the necessary number of ? 1s ? is counted and an hdlc controller on iom -2 requests upstream d-channel access (bac bit is set to 0), the arbiter allows this d-channel controller immediate access and blocks other tes on s (e-bits are inverted). similar as on the s-interface the priority for d-channel access on iom -2 can be configured to 8 or 10 (s_cmd.dprio). the configuration settings of the t-smint i in intelligent nt applications are summarized in table 12 . b1 b2 mon 0 d ci0 ic1 ic2 mon1 ci1 mx mr mx mr s/g a/b s/g a/b stop/go available/blocked itd09693.vsd dd pef 82902 functional description data sheet 55 2001-11-09 note: for mode selection in the s_mode register the mode1/2 bits are used to select intelligent nt mode, mode0 selects nt or lt-s state machine. with the configuration settings shown above the t-smint i in intelligent nt applications provides for equal access to the d-channel for terminals connected to the s-interface and for d-channel sources on iom -2. 2.3.5.5 state machine of the d-channel arbiter figure 30 gives a simplified view of the state machine of the d-channel arbiter. cnt is the number of ? 1 ? on the iom -2 d-channel and bac corresponds to the bac-bit on iom -2. the number n depends on configuration settings (selected priority 8 or 10) and the condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10, respectively) or if the last transmission was successful (n = 9 or 11, respectively). table 12 t-smint i configuration settings in intelligent nt applications functional block configuration description configuration setting layer 1 select intelligent nt mode s-transceiver mode register: s_mode.mode0 = 0 (nt state machine) or s_mode.mode0 = 1 (lt-s state machine) s_mode.mode1 = 1 s_mode.mode2 = 1 layer 2 enable s/g bit and tic bus evaluation d-channel mode register: modeh.dim2-0 = 001 pef 82902 functional description data sheet 56 2001-11-09 figure 30 state machine of the d-channel arbiter (simplified view) 1) 1. local d-channel controller transmits upstream in the initial state ( ? ready ? state) neither the local d-channel sources nor any of the terminals connected to the s-bus transmit in the d-channel. the t-smint i s-transceiver thus receives bac = ? 1 ? (iom -2 du line) and transmits s/g = ? 1 ? (iom -2 dd line). the access will then be established according to the following procedure: local d-channel source verifies that bac bit is set to one (currently no bus access). local d-channel source issues tic bus address and verifies that no controller with higher priority requests transmission (tic bus access must always be performed even if no other d-channel sources are connected to iom -2). local d-channel source issues bac = ? 0 ? to block other sources on iom -2 and to announce d-channel access. t-smint i s-transceiver pulls s/g bit to zero ( ? local access ? state) as soon as cnt n (see note) to allow sending d-channel data from the entitled source. 1) if the s-transceiver is reset by sres.res_s = ? 1 ? or disabled by s_conf0.dis_tr = ? 1 ? , then the d-channel arbiter is in state ready (s/g = ? 1 ? ), too. the s/g evaluation of the hdlc has to be disabled in this case; otherwise, the hdlc is not able to send data. bac = 1 & dci = 0 ready s/g = 1 e = d 1)2) rst=0, a/b=0, mode=0xx d-channel_arbitration.vsd bac = d.c. dci = 0 s access s/g = 1 e = d 1) & cnt n (bac=0 or dci=1) (bac=1 & dci=0) cnt 6 (cnt 2 & d=0) & [bac = 1 or (bac = 0 & cnt < n)] 1) setting dci = 1 causes e = d 2) setting a/b = 0 causes e = d bac = 0 or dci = 1 local access wait for start flag s/g = 0 e = d cnt = 6 bac = d.c. dci = d.c. local access transmit / stop flag s/g = 0 e = d bac dci state s/g e in out pef 82902 functional description data sheet 57 2001-11-09 t-smint i s-transceiver transmits inverted echo channel (e bits) on the s-bus to block all connected s-bus terminals (e = d ). local d-channel source commences with d data transmission on iom -2 as long as it receives s/g = ? 0 ? . after d-channel data transmission is completed the controller sets the bac bit to one. t-smint i s-transceiver transmits non-inverted echo (e = d). t-smint i s-transceiver pulls s/g bit to one ( ? ready ? state) to block the d-channel controller on iom -2. note: if right after d-data transmission the d-channel arbiter goes to state ?ready? and the local d-channel source wants to transmit again, then it may happen that the leading ?0? of the start flag is written into the d-channel before the d-channel source recognizes that the s/g bit is pulled to ?1? and stops transmission. in order to prevent unintended transitions to state ?s-access?, the additional condition cnt 2 is introduced. as soon as cnt n, the s/g bit is set to ?0? and the d-channel source may start transmission again (if tic bus is occupied). this allows an equal access for d-channel sources on iom -2 and on the s interface. 2. terminal transmits d-channel data upstream the initial state is identical to that described in the last paragraph. when one of the connected s-bus terminals needs to transmit in the d-channel, access is established according to the following procedure: s-transceiver recognizes that the d-channel on the s-bus is active via d = ? 0 ? . s-transceiver transfers s-bus d-channel data transparently through to the upstream iom -2 bus. 2.3.6 activation/deactivation of iom ? -2 interface the deactivation procedure of the iom -2 interface is shown in figure 31. after detecting the code di (deactivation indication) the t-smint i responds by transmitting dc (deactivation confirmation) during subsequent frames and stops the timing signals after the fourth frame. the clocks stop at the end of the c/i-code in iom -2 channel 0. pef 82902 functional description data sheet 58 2001-11-09 figure 31 deactivation of the iom ? -2 clocks conditions for power-down if none of the following conditions is true, the iom -2 interface can be switched off, reducing power consumption to a minimum. s-transceiver is not in state ? deactivated ? signal info0 on the s-interface uk0-transceiver is not in state ? deactivated ? pin du is low (either at the iom -2 interface or via iom_cr.spu) external pin eaw external awake is low bit mode 1.cfs = ? 0 ? stop on the correct place in the iom -2 frame. dcl must be low during power down (stop on falling edge of dcl) (see figure 31 ). a deactivated iom -2 can be reactivated by one of the following methods: pulling pin du line low: ? directly at the iom -2 interface ? via the p interface with "software power up" (iom_cr:spu bit) pulling pin eaw ? external awake ? low setting ? configuration select ? mode1:cfs bit = ? 0 ? level detection at the s-interface itd10292 di di di di di di fsc din dout dc dc dc dc dr dr detail see fig.b din dcl dc/ ? / c / c / c deactivated deactivated a) b) r iom -2 interface iom -2 interface r pef 82902 functional description data sheet 59 2001-11-09 activation from the u-interface 2.4 u-transceiver the statemachine of the u-transceiver is compatible to the nt state machine in the peb 8090 documentation [9], but includes some minor changes for simplification and compliance to ref. [1]. the u-transceiver is configured and controlled via the registers described in chapter . the u-transceiver is always in iom -2 channel 0. 2.4.1 4b3t frame structure the 4b3t u-interface performs full duplex data transmission and reception at the u- reference point according to etsi ts 102 080 and ftz 1tr 220. it applies the 4b3t block code together with adaptive echo cancelling and equalization. transmission performance shall be such, that it meets all etsi and ftz test loops with margin. the u-interface is designed for data transmission on twisted pair wires in local telephone loops, with basic access to isdn and a user bit rate of 144 kbit/s. the following information is transmitted over the twisted pair: bidirectional: ? b1, b2, d data channels ? 120 khz symbol clock ? 1 khz frame ? activation ? 1 kbit/s transparent channel (m symbol), (not implemented) from lt to nt side: ? power feeding ? deactivation ? remote control of test loops (m symbol) from nt to lt side: ? indication of monitored code violations (m symbol) performance requirements according to ftz 1 tr 220 (august 1991): on the u-interface, the following transmission ranges are achieved without additional signal regeneration on the loop (bit error rate 10 -7 ): with noise : 4.2 km on wires of 0.4 mm diameter and 8 km on 0.6 mm wires without noise : 5 km on wires of 0.4 mm diameter and 10 km on 0.6 mm wires note: typical attenuation of ftz wires of 0.4 mm diameter is about 7db/km in contrast to etsi wires of 0.4 mm with about 8db/km. the transmission ranges can be doubled by inserting a repeater for signal regeneration. pef 82902 functional description data sheet 60 2001-11-09 performance requirements according to etsi ts 102 080 are met, too. 1 ms frames are transmitted via the u-interface, each consisting of: 108 symbols: 144 bit scrambled and coded b1 + b2 + d data 11 symbols: barker code for both symbol and frame synchronization (not scrambled) 1 symbol: ternary maintenance symbol (not scrambled) the 108 user data symbols are split into four equally structured groups. each group (27 ternary symbols, resp. 36 bits) contains the user data of two iom ? -2 frames in the same order (8b + 8b + 2d + 8b + 8b + 2d). different syncwords are used for each direction: downstream from lt to nt + + + ? ? ? + ? ? + ? upstream from nt to lt ? + ? ? + ? ? ? + + + on the nt side, the transmitted barker code begins 60 symbols after the received barker code and vice versa. d 1 ... d 8 ternary 2b + d data of iom ? -2 frames 1 ... 8 m maintenance symbol +, ? syncword pef 82902 functional description data sheet 61 2001-11-09 table 13 frame structure a for downstream transmission lt to nt 123456789101112 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 d 1 13 14 15 16 17 18 19 20 21 22 23 24 d 1/2 d 1/2 d 1/2 d 2 d 2 d 2 d 2 d 2 d 2 d 2 d 2 d 2 25 26 27 28 29 30 31 32 33 34 35 36 d 2 d 2 d 2 d 3 d 3 d 3 d 3 d 3 d 3 d 3 d 3 d 3 37 38 39 40 41 42 43 44 45 46 47 48 d 3 d 3 d 3 d 3/4 d 3/4 d 3/4 d 4 d 4 d 4 d 4 d 4 d 4 49 50 51 52 53 54 55 56 57 58 59 60 d 4 d 4 d 4 d 4 d 4 d 4 d 5 d 5 d 5 d 5 d 5 d 5 61 62 63 64 65 66 67 68 69 70 71 72 d 5 d 5 d 5 d 5 d 5 d 5 d 5/6 d 5/6 d 5/6 d 6 d 6 d 6 73 74 75 76 77 78 79 80 81 82 83 84 d 6 d 6 d 6 d 6 d 6 d 6 d 6 d 6 d 6 d 7 d 7 d 7 85 86 87 88 89 90 91 92 93 94 95 96 m d 7 d 7 d 7 d 7 d 7 d 7 d 7 d 7 d 7 d 7/8 d 7/8 97 98 99 100 101 102 103 104 105 106 107 108 d 7/8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 d 8 109 110 111 112 113 114 115 116 117 118 119 120 d 8 +++???+??+? pef 82902 functional description data sheet 62 2001-11-09 u 1 ... u 8 ternary 2b + d data of iom ? -2 frames 1... 8 m maintenance symbol +, - syncword table 14 frame structure b for upstream transmission nt to lt 123456789101112 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 u 1 13 14 15 16 17 18 19 20 21 22 23 24 u 1/2 u 1/2 u 1/2 u 2 u 2 u 2 u 2 u 2 u 2 u 2 u 2 u 2 25 26 27 28 29 30 31 32 33 34 35 36 m u 2 u 2 u 2 u 3 u 3 u 3 u 3 u 3 u 3 u 3 u 3 37 38 39 40 41 42 43 44 45 46 47 48 u 3 u 3 u 3 u 3 u 3/4 u 3/4 u 3/4 u 4 u 4 u 4 u 4 u 4 49 50 51 52 53 54 55 56 57 58 59 60 u 4 ?+??+???+++ 61 62 63 64 65 66 67 68 69 70 71 72 u 4 u 4 u 4 u 4 u 4 u 4 u 5 u 5 u 5 u 5 u 5 u 5 73 74 75 76 77 78 79 80 81 82 83 84 u 5 u 5 u 5 u 5 u 5 u 5 u 5/6 u 5/6 u 5/6 u 6 u 6 u 6 85 86 87 88 89 90 91 92 93 94 95 96 u 6 u 6 u 6 u 6 u 6 u 6 u 6 u 6 u 6 u 7 u 7 u 7 97 98 99 100 101 102 103 104 105 106 107 108 u 7 u 7 u 7 u 7 u 7 u 7 u 7 u 7 u 7 u 7/8 u 7/8 u 7/8 109 110 111 112 113 114 115 116 117 118 119 120 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 u 8 pef 82902 functional description data sheet 63 2001-11-09 2.4.2 maintenance channel the 4b3t frame structure provides a 1 kbit/s m(aintenance)-channel for the transfer of remote loopback commands and error indications. loopback commands the lt station uses the m-channel to request remote loopbacks. loopback commands are coded with a series of ? 0 ? and ? + ? symbols. a continuous series of ? + ? requests for loopback 2 activation in the nt a continuous series of ? 0 ? requests for deactivation of any loopback the nt station reacts as soon as the pattern has been detected in 8 consecutive symbols. error indications the nt u-transceiver reports line code violations via the m-channel to the exchange by setting one m-bit to ? + ? polarity. transparent messages the exchange of transparent messages via the transparent channel is not supported by the t-smint i. 2.4.3 coding from binary to ternary data each 4 bit block of binary data is coded into 3 ternary symbols of mms 43 block code according to table 15 . the number of the next column to be used, is given at the right hand side of each block. the left hand signal elements in the table (both ternary and binary) are transmitted first. table 15 mms 43 coding table s1 s2 s3 s4 t t t t t 0 0010 ? +10 ? +20 ? +30 ? +4 0 111 ? 0+1 ? 0+2 ? 0+3 ? 0+4 0 100 ? +01 ? +02 ? +03 ? +04 0 010+ ? 01+ ? 02+ ? 03+ ? 04 1 011+0 ? 1+0 ? 2+0 ? 3+0 ? 4 1 1100+ ? 10+ ? 20+ ? 30+ ? 4 1 001+ ? +2+ ? +3+ ? +4 ??? 1 pef 82902 functional description data sheet 64 2001-11-09 2.4.4 decoding from ternary to binary data decoding is done in the reverse manner of coding. the received blocks of 3 ternary symbols are converted into blocks of 4 bits. the decoding algorithm is given in table 16 . as in the encoding table, the left hand symbol of each block (both binary and ternary) is the first bit and the right hand is the last. if a ternary block "0 0 0" is received, it is decoded to binary "0 0 0 0". this pattern usually occurs only during deactivation. 0 01100+200+300+4 ?? 02 1 1010+020+030+04 ? 0 ? 2 1 000+002+003+0040 ?? 2 0 110 ? ++2 ? ++3 ?? +2 ?? +3 1 010++ ? 2++ ? 3+ ?? 2+ ?? 3 1 111++0300 ? 100 ? 200 ? 3 0 000+0+30 ? 010 ? 020 ? 03 0 1010++3 ? 001 ? 002 ? 003 1 100+++4 ? + ? 1 ? + ? 2 ? + ? 3 table 16 4b3t decoding table ternary block binary block 0 0 0, + 0 +, 0 ? 0 0 0 0 0 0 ? + 0001 + ? 0 0 0 1 0 0 0 +, ? ? 0 0 0 1 1 ? + 0 0 1 0 0 0 + +, ? 0 0 0 1 0 1 ? + +, ? ? + 0 1 1 0 ? 0 + 0 1 1 1 + 0 0, 0 ? ? 1000 + ? +, ? ? ? 1001 + + ? ,+ ? ? 1010 + 0 ? 1011 + + +, ? + ? 1100 table 15 mms 43 coding table s1 s2 s3 s4 pef 82902 functional description data sheet 65 2001-11-09 2.4.4.1 monitoring of code violations the running digital sum monitor (rdsm) computes the running digital sum from the received ternary symbols by adding the polarity of the received user data (+ 1, 0, ? 1). at the end of each block, the running digital sum is supposed to reflect the number of the next column in table 15 . a code violation has occurred if the running digital sum is less than one or more than four at the end of a ternary block, or if the ternary block 0 0 0 (three user symbols with zero polarity) is found in the received data. if at the end of a ternary block no error was found, the running digital sum retains its current value. if the counter value is greater than 4, it is set to 4 at the beginning of the next ternary block, if its value is 0 or less, it is set to one. so after a code violation has been detected, the rdsm synchronizes itself within a period depending on the received data pattern. note there are some transmission errors which do not cause a code violation. 2.4.4.2 block error counter (rds error counter) the t-smint i provides a block error counter. this feature allows monitoring the transmission quality on the u-interface. on the nt side a block error is given, if a u-frame with at least one code violation has been detected (near-end block error). in the following frame the nt transmits a positive m-symbol upstream. on the lt side a block error is given, if a u-frame with at least one code violation has been detected (near-end block error) or a positive m-symbol has been received from the nt (far-end block error). the current status of the block error counter can be retrieved by the system interface. when the block error counter is read (register rds), it is automatically reset. the counter is enabled in all states listed in table 17 and reset in all other states. the counter is saturated at its maximum value (255). 0 + 0, ? 0 ? 1101 0 + ? 1110 + + 0, 0 0 ? 1111 table 17 active states sbc sychronizing wait for info u4h transparent table 16 4b3t decoding table pef 82902 functional description data sheet 66 2001-11-09 note that every frame with a detected code violation causes about 10 to 20 binary bit errors on average. so a bit error rate of 10 ? 7 in both directions is equivalent to 2 detected frame errors within 1000 s in the lt (1 frame error detected in the nt and transmitted via m-symbol). 2.4.5 scrambler / descrambler scrambler the binary transmit data from the iom ? -2 interface is scrambled with a polynomial of 23 bits, before it is sent to the 4b3t coder. the scrambler polynomial is:: descrambler the received data (after decoding from ternary to binary) is multiplied with a polynomial of 23 bits in order to recover the original data before it is forwarded to the iom ? -2 interface.the descrambler is self synchronized after 23 symbols. the descrambler polynomial is:: the scrambling / descrambling process is controlled fully by the t-smint i. hence, no influence can be taken by the user. 2.4.6 command/indication codes both commands and indications depend on the data direction. table 18 presents all defined c/i codes. a new command or indication will be recognized as valid after it has been detected in two successive iom ? -2 frames (double last-look criterion). note: unconditional c/i-commands must be applied for at least 4 iom ? -2 frames for reliable recognition by the u-transceiver. indications are strictly state orientated. refer to the state diagrams in the following sections for commands and indications applicable in various states. table 18 c/i codes code in out 0000 tim dr 0001 ?? 0010 ?? z 23 ? z 18 ? 1 ++ z 23 ? z 5 ? 1 ++ pef 82902 functional description data sheet 67 2001-11-09 2.4.7 state machine for activation and deactivation 2.4.7.1 state machine notation the following state diagram describes all the actions/reactions resulting from any command or detected signal and resulting from the various operating modes. the states with its inputs and outputs are interpreted as shown below: 0011 ltd ? 0100 ? rsy 0101 ssp ? 0110 dt ? 0111 ?? 1000 ar ar 1001 reserved 1) ? 1010 ? arl 1011 ?? 1100 ai ai 1101 res ? 1110 ? ail 1111 di dc 1) c/i code ? 1010 ? must not be input to the u-transceiver. ai activation indication di deactivation indication. ail activation indication loop 2 dr deactivation request ar activation request ltd lt disable arl activation request local loop res reset dt data through mode rsy resynchronization indication dc deactivation confirmation ssp send-single-pulses tim timing request pef 82902 functional description data sheet 68 2001-11-09 figure 32 state diagram example each state has one or more transitions to other states. these transitions depend on certain conditions which are noted next to the transition lines. these conditions are the only possibility to leave a state. if more conditions have to be fulfilled together, they are put into parentheses with an and operator (&). if more than one condition leads to the same transition, they are put into parentheses with an or operator (|). the meaning of a condition may be inverted by the not operator (/). only the described states and transitions exist. at some transitions, an internal timer is started. the start of a timer is indicated by txs ( ? x ? is the timer number). transitions that are caused if a timer has expired are labelled by txe. some conditions lead to the same target state. to reduce the number of lines and the complexity of the figures, a state named ? any state ? acts on behalf of all state. the state machines are designed to cope with all isdn devices with iom ? -2 standard interfaces. undefined situations are excluded. in any case, the involved devices will enter defined conditions as soon as the line is deactivated. 2.4.7.2 awake protocol for the awake process two signals are defined ? u1w ? and ? u2w ? . depending on the call direction (up-, downstream) u1w and u2w are interpreted as awake or acknowledge signals (see figures below). c/i channel indication (dout) out in state name transmitted u-signal sm_expl.emf pef 82902 functional description data sheet 69 2001-11-09 figure 33 awake procedure initiated by the lt figure 34 awake procedure initiated by the nt acting as calling station after sending the awake signal, the awaking u-transceiver waits for the acknowledge. after 12 ms, the awake signal is repeated, if no acknowledge has been recognized. if an acknowledge signal has been recognized, the u-transceiver waits for its possible repetition (in case of previous coincidence of two awake signals). if no repetition was detected, the u-transceiver starts transmitting u2 with a delay of 7 ms. if such a repetition is detected, the u-transceiver interprets it as an awake signal and behaves like a device awoken by the far end. 2.133 ms info u2w lt info u2 (a) 2.133 ms info u1w nt info u1a 12 ms 7 ms 13 ms itd06385.vsd 2.133 ms info u1w nt 13 ms info u1a 6 ms 2.133 ms info u2w lt info u2 (a) 7 ms itd06386.vsd pef 82902 functional description data sheet 70 2001-11-09 acknowledging a wake-up call if a deactivated device detects an awake signal on u, an acknowledge signal is sent out. after that, the u-transceiver waits for a possible repetition of the awake signal (in case the acknowledge hasn ? t been recognized). if no repetition is found, the awoken u-transceiver starts sending u2 after 7 ms from detecting the awake signal. if a repeated awake signal is found, the procedure in the awoken u-transceiver starts again. pef 82902 functional description data sheet 71 2001-11-09 2.4.7.3 nt state machine (iec-t / ntc-t compatible) figure 35 nt state machine (iec-t/ntc-t compatible) note: the test modes ?data through? (dt) and ?send single pulses? (ssp) are invoked via c/i codes ?dt? and ?ssp? according to table 18 . setting sres.res_u to ?1? forces the u-transceiver into test mode ?quiet mode? (qm), i.e. the u-transceiver is hardware reset. awr any state awr dt awr awake signal sent rsy ack. sent / received rsy u0, da ar awt start awaking uk0 rsy iom awaked dc t6e awt sending awake-ack. rsy tim awr deactivated dc deactivating dc ar di awr t05e u0 t6s t05s t6s u1w u0 t13s u0 u1w t13s t05s t13s u0 u0 res ssp or ltd (di & t05e) t05s nt_sm_4b3t_cust.emf di t6s rsy loss of framing u0 u0 u0 u0 pend. deactivation dr u0 (u0 & t12e) u2 t12s t13e ai u4h ar / arl sbc synchronizing u1 ar / arl wait for info u4h u3 transparent ai / ail u5 lof lof lof u0 t05s reset dr u0 di test dr sp / u0 synchronizing rsy u1a pef 82902 functional description data sheet 72 2001-11-09 2.4.7.4 inputs to the u-transceiver c/i-commands ai activation indication the downstream device issues this indication to announce that layer 1 is available. the u-transceiver in turn informs the lt side by transmitting u3. ar activation request the u-transceiver is requested to start the activation process (if not already done) by sending the wake-up signal u1w. di deactivation indication this indication is used during a deactivation procedure to inform the u- transceiver that it may enter the ? deactivated ? (power-down) state. dt data through test mode this unconditional command is used for test purposes only and forces the u- transceiver into state ? transparent ? . table 19 differences to the former nt-sm of the iec-t/ntc-t no. state/ signal change comment 1. state ? deact. request rec. ? split into 3 states - ? pend. deactivation 1 ? - ? reset ? state - ? test ? state simplifies sm implementation 2. state ? loss of framing ? new inserted, results in different behavior in state ? transparent ? , no return to normal transmission possible after detection of lof compliance to etsi ts 102 080, corresponds to state nt1.10 3. c/i-code ltd new inserted 4. state ? power down ? renamed to state ? deactivated ? for consistency reasons to 2b1q 5. state ? data transmission ? renamed to state ? transparent ? 6. timer variables introduced name duration see table 20 pef 82902 functional description data sheet 73 2001-11-09 ltd lt disable this unconditional command forces the u-transceiver to state ? test ? , where it transmits u0. no further action is initiated. res reset unconditional command which resets the u-transceiver. ssp send single pulses unconditional command which requests the transmission of single pulses on the u-interface. tim timing the u-transceiver is requested to enter state ? iom awaked ? . u-interface events u0 u0 detected u0 is recognized after 120 symbols (1ms) with zero level in a row. detection may last up to 2 ms. u2 u2 detected the u-transceiver detects u2 if continuous binary 0 ? s are found after descrambling and lof = 0 for at least 8 subsequent u-frames. u2 is detected after 8 to 9 ms. u4h u4h detected u4h is recognized, if the u-transceiver detects 16 subsequent binary 1 ? s after descrambling. awr awake signal (u2w) detected awt awake signal (u1w) has been sent out lof loss of framing on u-interface txe timer ended, the started timer has expired timers the start of timers is indicated by txs, the expiry by txe. the following table shows which timers are used. table 20 timers timer duration (ms) function state t05 0.5 c/i code recognition pend. deactivation, deactivating t6 6 supervises u1w repetition start awaking uk0 pef 82902 functional description data sheet 74 2001-11-09 2.4.7.5 outputs of the u-transceiver below the signals and indications are summarized that are issued on iom ? -2 (c/i indications) and on the u-interface (predefined u-signals). c/i indications ai activation indication the u-transceiver has established transparency of transmission. the downstream device is requested to establish layer-1 functionality. ail activation indication loop-back the u-transceiver has established transparency of transmission. the downstream device is requested to establish a loopback #2. ar activation request the downstream device is requested to start the activation procedure. arl activation request loop-back the u-transceiver has detected a loop-back 2 command in the m-channel and has established transparency of transmission in the direction iom ? to u- interface. the downstream device is requested to start the activation procedure and to establish a loopback #2. dc deactivation confirmation idle code on the iom ? -2 interface. dr deactivation request the u-transceiver has detected a deactivation request command from the lt- side for a complete deactivation. the downstream device is requested to start the deactivation procedure. rsy resynchronizing indication rsy informs the downstream device that the u-transceiver is not synchronous. t12 12 prevents the u-transceiver in state synchronizing from immediate transition to state ? pend. deactivation ? if u0 is detected synchronizing t13 13 supervises u2w repetition ack. sent / received sending awake-ack. table 20 timers (cont ? d) timer duration (ms) function state pef 82902 functional description data sheet 75 2001-11-09 signals on u-interface the signals u0, u1w, u1a, u1, u3, u5 and sp are transmitted on the u-interface.they are defined in table 25 . signals on iom ? -2 the data (b+b+d) is set to all ? 1 ? s in all states besides the states listed in table 17 . dependence of outputs the m-symbol output in states with valid m-symbol output its value is set according to table 21 : 2.4.7.6 nt-states in this section each state is described with its function. acknowledge sent / receive after having sent the awake signal, the u-transceiver has received the acknowledge wake tone. if being awoken the u-transceiver has sent the acknowledge. in both cases the u-transceiver waits for possible repetition or time-out. table 21 m symbol output rds error not detected detected m symbol output ? 0 ? ? + ? table 22 signal output on uk0 in state test input c/i-code ssp applied all other except c/i-code ? di ? signal output on uk0 sp u0 table 23 c/i-code output loopback command sbc synchronizing wait for info u4h transparent not received ar ar ai received arl arl ail pef 82902 functional description data sheet 76 2001-11-09 awake signal sent the nt has sent out the awake signal u1w and waits now for a response. if the lt does not react in time timer t6 expires and the nt repeats its wake-up call. deactivated only in ? deactivated ? state the device may enter the power-down mode. deactivating state deactivating assures that the c/i-channel code dc is issued four times before entering the ? deactivated ? state. iom ? awaked the u-transceiver is deactivated, but may not enter the power-down mode. loss of framing this state is entered on loss of framing (lof). no signal is transmitted on the u-interface. a receiver-reset is performed by. note that there is no return to the ? transparent ? state that has been possible before in the former iec-t based state machine. pending deactivation the u-transceiver has received u0. the u-transceiver remains at least 0.5ms in this state before it accepts di. sbc synchronizing the nt is now synchronized and indicates this by ar/arl towards the downstream device. the nt waits for the acknowledge ? ai ? from the downstream device. sending awake-ack. on the receipt of the awake signal u2w the u-transceiver responds with the transmission of u1w. start awaking uk0 on the receipt of ar in the c/i-channel the u-transceiver sends the awake signal u1w to start an activation. pef 82902 functional description data sheet 77 2001-11-09 synchronizing after the successful awake procedure the u-transceiver trains its receiver coefficients until it is able to detect the signals u2. reset in state ? reset ? a software-reset is performed. test state ? test ? is entered when the unconditional commands c/i=ssp is applied. the test signal ssp is issued as long as pin ssp is active or c/i=ssp is applied. transparent the transmission line is fully activated. user data is transparently exchanged by u4/u5. transparent state is entered in the case of a loopback 2. the downstream device is informed by c/i code ai that the transparent state has been reached note that in contrast to the former iec-t state machine there is no resynchronization mechanism. once loss of framing (lof) has been detected a deactivation is initiated. wait for info u4h the nt is synchronized and waits now for the permission (u4h) to go to the ? transparent ? state. 2.4.8 u-transceiver interrupt structure the u-interrupt status register (istau) contains the interrupt sources of the u- transceiver ( figure 36 ). each source can be masked by setting the corresponding bit of the u-interrupt mask register (masku) to ? 1 ? . such masked interrupt status bits are not indicated when istau is read and do not generate an interrupt request. the istau register is cleared on read access. the interrupt sources of the istau register (ucir, rds, 1ms) need not be evaluated. when at time t1 an interrupt source generates an interrupt, all further interrupts are collected. reading the istau register clears all interrupts set before t1, even if masked. all interrupts, which are flagged after t1 remain active. after the istau read access, the next unmasked interrupt will generate the next interrupt at time t2. after t2 it is possible to reprogram the masku register, so that all interrupts, which arrived between t1 and t2 are accessible. pef 82902 functional description data sheet 78 2001-11-09 i figure 36 interrupt structure u-transceiver u s ... ... ... ... ... ... ista mask int intstruct_4b3t.emf 0 ci 0 0 1ms 1 ci 1 1 1ms 0 7 ucir 0 7 0 0 0 0 c/i c/i c/i c/i rds rds 0 0 1 1 istau masku pef 82902 functional description data sheet 79 2001-11-09 2.5 s-transceiver the s-transceiver offers the nt and lt-s mode state machines described in the user ? s manual v3.4 [8]. the s-transceiver lies in iom -2 channel 1 (default) and is configured and controlled via the registers described in chapter 4.5 . the state machine is set to nt mode (default) but can be set to lt-s mode via register programming. the te mode (s-transceiver te mode, u-transceiver disabled) is not supported. 2.5.1 line coding, frame structure line coding the following figure illustrates the line code. a binary one is represented by no line signal. binary zeros are coded with alternating positive and negative pulses with two exceptions: for the required frame structure a code violation is indicated by two consecutive pulses of the same polarity. these two pulses can be adjacent or separated by binary ones. in bus configurations a binary zero always overwrites a binary one. figure 37 s/t -interface line code frame structure each s/t frame consists of 48 bits at a nominal bit rate of 192 kbit/s. for user data (b1+b2+d) the frame structure applies to a data rate of 144 kbit/s (see figure 37 ). in the direction te nt the frame is transmitted with a two bit offset. for details on the framing rules please refer to itu i.430 section 6.3. the following figure illustrates the standard frame structure for both directions (nt te and te nt) with all framing and maintenance bits. 011 code violation pef 82902 functional description data sheet 80 2001-11-09 figure 38 frame structure at reference points s and t (itu i.430) note: the itu i.430 standard specifies s1 - s5 for optional use. ? f framing bit f = (0b) identifies new frame (always positive pulse, always code violation) ? l. d.c. balancing bit l. = (0b) number of binary zeros sent after the last l. bit was odd ? d d-channel data bit signaling data specified by user ? e d-channel echo bit e = d received e-bit is equal to transmitted d-bit ? f a auxiliary framing bit see section 6.3 in itu i.430 ? nn = ? b1 b1-channel data bit user data ? b2 b2-channel data bit user data ? a activation bit a = (0b) info 2 transmitted a = (1b) info 4 transmitted ? s s-channel data bit s 1 channel data (see note below) ? m multiframing bit m = (1b) start of new multi-frame f a pef 82902 functional description data sheet 81 2001-11-09 2.5.2 s/q channels, multiframing according to itu recommendation i.430 a multi-frame provides extra layer-1 capacity in the te-to-nt direction through the use of an extra channel between the te and nt (q- channel). the q bits are defined to be the bits in the f a bit position. in the nt-to-te direction the s-channel bits are used for information transmission. the s- and q-channels are accessed via c by reading/writing the sqr or sqx bits in the s/q channel registers (sqrr, sqxr). table 24 shows the s and q bit positions within the multi-frame. table 24 s/q-bit position identification and multi-frame structure the s-transceiver starts multiframing if sqxr1.mfen is set. after multi-frame synchronization has been established in the te, the q data will be inserted at the upstream (te nt) f a bit position by the te in each 5th s/t frame, the frame number nt-to-te f a bit position nt-to-te m bit nt-to-te s bit te-to-nt f a bit position 1 2 3 4 5 one zero zero zero zero one zero zero zero zero s11 s21 s31 s41 s51 q1 zero zero zero zero 6 7 8 9 10 one zero zero zero zero zero zero zero zero zero s12 s22 s32 s42 s52 q2 zero zero zero zero 11 12 13 14 15 one zero zero zero zero zero zero zero zero zero s13 s23 s33 s43 s53 q3 zero zero zero zero 16 17 18 19 20 one zero zero zero zero zero zero zero zero zero s14 s24 s34 s44 s54 q4 zero zero zero zero 1 2 one zero one zero s11 s21 q1 zero pef 82902 functional description data sheet 82 2001-11-09 s data will be inserted at the downstream (nt te) s bit position in each 5th s/t frame (see table 24 ). access to s2-s5-channel is not supported. interrupt handling for multi-framing to trigger the microcontroller for a multi-frame access an interrupt can be generated once per multi-frame (sqw) or if the received q-channel have changed (sqc). in both cases the microcontroller has access to the multiframe within the duration of one multiframe (5 ms). the start of a multiframe can not be synchronized to an external signal. 2.5.3 data transfer between iom -2 and s 0 in the state g3 (activated) or if the internal layer-1 statemachine is disabled and xinf of register s_cmd is programmed to ? 011 ? the b1, b2 and d bits are transferred transparently from the s/t to the iom -2 interface and vice versa. in all other states ? 1 ? s are transmitted to the iom -2 interface. note: in intelligent nt or intelligent lt-s mode the d-channel access can be blocked by the iom -2 d-channel handler. 2.5.4 loopback 2 c/i commands arl and ail close the analog loop as close to the s-interface as possible. etsi refers to this loop under ? loopback 2 ? . etsi requires, that b1, b2 and d channels have the same propagation delay when being looped back. the d-channel echo bit is set to bin. 0 during an analog loopback (i.e. loopback 2). the loop is transparent. note: after c/i-code ail has been recognized by the s-transceiver, zeros are looped back in the b and d-channels (du) for four frames. 2.5.5 control of s-transceiver / state machine the s-transceiver activation/ deactivation can be controlled by an internal statemachine via the iom -2 c/i-channel or by software via the c interface directly. in the default state the internal layer-1 statemachine of the s-transceiver is used. by setting the l1sw bit in the s_conf0 register the internal statemachine can be disabled and the layer-1 transmit commands, which are normally generated by the internal statemachine can be written directly into the s_cmd register or the received status read out from the s_sta register, respectively. the s-transceiver layer-1 control flow is shown in figure 39 . pef 82902 functional description data sheet 83 2001-11-09 figure 39 s-transceiver control the state diagram notation is given in figure 40 . the information contained in the state diagrams are: ? state name ? signal received from the line interface (info) ? signal transmitted to the line interface (info) ? c/i code received (commands) ? c/i code transmitted (indications) ? transition criteria the transition criteria are grouped into: ? c/i commands ? signals received from the line interface (infos) ? reset iom-2 layer-1 control layer-1 state machine macro_14 transmit info transmitter receiver receive info command register for transmitter (s_cmd) status register of receiver (s_sta) c/i command c/i indication c-interface disable internal statemachine (s_conf.l1sw) pef 82902 functional description data sheet 84 2001-11-09 figure 40 state diagram notation as can be seen from the transition criteria, combinations of multiple conditions are possible as well. a ? ? ? stands for a logical and combination. and a ? + ? indicates a logical or combination. test signals 2 khz single pulses (tm1) one pulse with a width of one bit period per frame with alternating polarity. 96 khz continuous pulses (tm2) continuous pulses with a pulse width of one bit period. note: the test signals tm1 and tm2 are invoked via c/i codes ?tm1? and ?tm2? according to chapter 2.5.5.1 . external layer-1 statemachine instead of using the integrated layer-1 statemachine it is also possible to implement the layer-1 statemachine completely in software. the internal layer-1 statemachine can be disabled by setting the l1sw bit in the s_conf0 register to ? 1 ? . the transmitter is completely under control of the microcontroller via register s_cmd. the status of the receiver is stored in register s_sta and has to be evaluated by the microcontroller. this register is updated continuously. if not masked a ric interrupt is generated by any change of the register contents. the interrupt is cleared after a read access to this register. reset states after an active signal on the reset pin rst the s-transceiver state machine is in the reset state. iom-2 interface c/i code macro_17.vsd state ind. cmd. i x i r s/t interface info in out unconditional transition pef 82902 functional description data sheet 85 2001-11-09 c/i codes in reset state in the reset state the c/i code 0000 (tim) is issued. this state is entered either after a hardware reset (rst ) or with the c/i code res. c/i codes in deactivated state if the s-transceiver is in state ? deactivated ? and receives i0 , the c/i code 0000 (tim) is issued until expiration of the 8 ms timer. otherwise, the c/i code 1111 (di) is issued. 2.5.5.1 c/i codes the table below presents all defined c/i0 codes. a command needs to be applied continuously until the desired action has been initiated. indications are strictly state orientated. refer to the state diagrams in the following sections for commands and indications applicable in various states. code lt-s nt cmdind cmdind 0000dr tim dr tim 0001res ? res ? 0010tm1 ? tm1 ? 0011tm2 ? tm2 ? 0100 ? rsy rsy rsy 0101 ???? 0110 ???? 0111 ???? 1000ar ar ar ar 1001 ???? 1010arl ? arl ? 1011 ? cvr ? cvr 1100 ? ai ai ai 1101 ???? 1110 ?? ail ? 1111dc di dc di pef 82902 functional description data sheet 86 2001-11-09 receive infos on s/t i0 info 0 detected i0 level detected (signal different to i0) i3 info 3 detected i3 any info other than info 3 transmit infos on s/t i0 info 0 i2 info 2 i4 info 4 it send single pulses (tm1). send continuous pulses (tm2). pef 82902 functional description data sheet 87 2001-11-09 2.5.5.2 state machine nt mode figure 41 state machine nt mode note: state ?test mode? can be entered from any state except from state ?test mode? itself, i.e. c/i-code ?tmi? must not be followed by c/i-code ?tmj? directly. g2 pend. act ar ard i2 i3 reset tim res i0 * g1 i0 detected ar dc i0 * g2 lost framing s/t rsy aid ard i2 i3 g1 deactivated di tim dc i0 i0 statem_nt_s.vsd g4 pend. deact. tim dr i0 i0 test mode i tim tm1 tm2 it * dr dr g4 wait for dr di dr i0 * (i0*16ms)+32ms dc dc tm1 tm2 any state dr dc any state res ard 1) ard 1) dr i3 i3*aid 2) rst ard 1) g2 wait for aid ai ard i2 i3 g3 lost framing u rsy rsy i2 * g3 activated ai aid i4 i3 ard 1) aid 2) i3*ard 1) i3*ard dr dr dr rsy rsy dr rsy ard 1) aid 2) 1) : ard = ar or arl 2) : aid =ai or ail ard 1) i3*aid 2) (i0*8ms) pef 82902 functional description data sheet 88 2001-11-09 g1 deactivated the s-transceiver is not transmitting. there is no signal detected on the s/t-interface, and no activation command is received in the c/i channel. activation is possible from the s/t interface and from the iom -2 interface. g1 i0 detected an info 0 is detected on the s/t-interface, translated to an ? activation request ? indication in the c/i channel. the s-transceiver is waiting for an ar command, which normally indicates that the transmission line upstream is synchronized. g2 pending activation as a result of the ard command, an info 2 is sent on the s/t-interface. info 3 is not yet received. in case of arl command, loop 2 is closed. g2 wait for aid info 3 was received, info 2 continues to be transmitted while the s-transceiver waits for a ? switch-through ? command aid from the device upstream. g3 activated info 4 is sent on the s/t-interface as a result of the ? switch through ? command aid: the b and d-channels are transparent. on the command ail, loop 2 is closed. g2 lost framing s/t this state is reached when the transceiver has lost synchronism in the state g3 activated. g3 lost framing u on receiving an rsy command which usually indicates that synchronization has been lost on the transmission line, the s-transceiver transmits info 2. g4 pending deactivation this state is triggered by a deactivation request dr, and is an unstable state. indication di (state ? g4 wait for dr ? ) is issued by the transceiver when: either info0 is received for a duration of 16 ms or an internal timer of 32 ms expires. pef 82902 functional description data sheet 89 2001-11-09 g4 wait for dr final state after a deactivation request. the s-transceiver remains in this state until dc is issued. unconditional states test mode tm1 send single pulses test mode tm2 send continuous pulses c/i commands command abbr. code remark deactivation request dr 0000 deactivation request. initiates a complete deactivation by transmitting info 0. reset res 0001 reset of state machine. transmission of info0. no reaction to incoming infos. res is an unconditional command. send single pulses tm1 0010 send single pulses. send continuous pulses tm2 0011 send continuous pulses. receiver not synchronous rsy 0100 receiver is not synchronous activation request ar 1000 activation request. this command is used to start an activation. activation request loop arl 1010 activation request loop. the transceiver is requested to operate an analog loop-back close to the s/t-interface. activation indication ai 1100 activation indication. synchronous receiver, i.e. activation completed. pef 82902 functional description data sheet 90 2001-11-09 activation indication loop ail 1110 activation indication loop deactivation confirmation dc 1111 deactivation confirmation. transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of info 0 enabled). indication abbr. code remark timing tim 0000 interim indication during deactivation procedure. receiver not synchronous rsy 0100 receiver is not synchronous. activation request ar 1000 info 0 received from terminal. activation proceeds. illegal code ciolation cvr 1011 illegal code violation received. this function has to be enabled in s_conf0.en_icv. activation indication ai 1100 synchronous receiver, i.e. activation completed. deactivation indication di 1111 timer (32 ms) expired or info 0 received for a duration of 16 ms after deactivation request. command abbr. code remark pef 82902 functional description data sheet 91 2001-11-09 2.5.5.3 state machine lt-s mode figure 42 state machine lt-s mode note: state ?test mode? can be entered from any state except from state ?test mode? itself, i.e. c/i-code ?tmi? must not be followed by c/i-code ?tmj ?directly. g3 activated ai dc ard i4 i3 reset tim res i0 * g2 pend. act. ar dc ard i2 i3 g2 lost framing s/t rsy dc ard i2 i3 g1 deactivated di tim dc i0 i0 1) : ard = ar or arl statem_lts_s.vsd g4 pend. deact. tim dr i0 i0 test mode i tim tm1 tm2 it * dr dr g4 wait for dr di dr i0 * (i0*16ms)+32ms dc dc tm1 tm2 any state dr dc any state res ard 1) ard 1) dr i3 dr dr i3 i3 rst (i0*8ms)+ard 1) pef 82902 functional description data sheet 92 2001-11-09 g1 deactivated the s-transceiver is not transmitting. there is no signal detected on the s/t-interface, and no activation command is received in the c/i channel. activation is possible from the s/t interface and from the iom -2 interface. g2 pending activation as a result of an info 0 detected on the s/t line or an ard command, the s-transceiver begins transmitting info 2 and waits for reception of info 3. the timer to supervise reception of info 3 is to be implemented in software. in case of an arl command, loop 2 is closed. g3 activated normal state where info 4 is transmitted to the s/t-interface. the transceiver remains in this state as long as neither a deactivation nor a test mode is requested, nor the receiver looses synchronism. when receiver synchronism is lost, info 2 is sent automatically. after reception of info 3, the transmitter keeps on sending info 4. g2 lost framing this state is reached when the s-transceiver has lost synchronism in the state g3 activated. g4 pending deactivation this state is triggered by a deactivation request dr. it is an unstable state: indication di (state ? g4 wait for dr. ? ) is issued by the s-transceiver when: either info0 is received for a duration of 16 ms, or an internal timer of 32 ms expires. g4 wait for dr final state after a deactivation request. the transceiver remains in this state until dc is issued. unconditional states test mode - tm1 single alternating pulses are sent on the s/t-interface. pef 82902 functional description data sheet 93 2001-11-09 test mode - tm2 continuous alternating pulses are sent on the s/t-interface. command abbr. code remark deactivation request dr 0000 dr - deactivation request. initiates a complete deactivation by transmitting info 0. reset res 0001 reset of state machine. transmission of info0. no reaction to incoming infos. res is an unconditional command. send single pulses tm1 0010 send single pulses. send continuous pulses tm2 0011 send continuous pulses. activation request ar 1000 activation request. this command is used to start an activation. activation request loop arl 1010 activation request loop. the transceiver is requested to operate an analog loop-back close to the s/t-interface. deactivation confirmation dc 1111 deactivation confirmation. transfers the transceiver into a deactivated state in which it can be activated from a terminal (detection of info 0 enabled). indication abbr. code remark timing tim 0000 interim indication during activation procedure in g1. receiver not synchronous rsy 0100 receiver is not synchronous activation request ar 1000 info 0 received from terminal. activation proceeds. illegal code ciolation cvr 1011 illegal code violation received. this function has to be enabled in s_conf0.en_icv. activation indication ai 1100 synchronous receiver, i.e. activation completed. deactivation indication di 1111 timer (32 ms) expired or info 0 received for a duration of 16 ms after deactivation request pef 82902 functional description data sheet 94 2001-11-09 2.5.6 s-transceiver enable / disable the layer-1 part of the s-transceiver can be enabled/disabled with the two bits s_conf0.dis_tr and s_conf2.dis_tx. if dis_tx= ? 1 ? the transmit buffers are disabled. the receiver will monitor for incoming data in this configuration. by default the transmitter is disabled (dis_tx = ? 1 ? ). if the transceiver is disabled (dis_tr = ? 1 ? , dis_tx = don ? t care) all layer-1 functions are disabled including the level detection circuit of the receiver. in this case the power consumption of the s-transceiver is reduced to a minimum. pef 82902 functional description data sheet 95 2001-11-09 2.5.7 interrupt structure s-transceiver figure 43 interrupt structure s-transceiver 0 0 0 0 ld ric sqc sqw 1 1 1 1 ld ric sqc sqw istas masks 0 7 reserved interr.vsd s ista mask int level detect sqx3 0 mfen 0 0 sqx1 sqx2 sqx4 msyn mfen 0 0 sqr1 sqr2 sqr3 sqr4 rinf 0 fecv 0 fsyn 0 ld s_sta sqrr sqxr 0 7 0 7 0 7 0 7 pef 82902 operational description data sheet 96 2001-11-09 3 operational description 3.1 layer 1 activation/deactivation 3.1.1 generation of 4b3t signal elements for control and monitoring purposes of the activation/deactivation progress the following signal elements are defined by ts 102 080 and ftz 1 tr 220. table 25 4b3t signal elements u0 no signal or deactivation signal that is used in both directions. downstream, it requests the nt to deactivate. upstream, the nt acknowledges by u0 that it is deactivated. u1w, u2w awake or awake acknowledge signal used in the awake procedure of the u-interface. u2 the lt sends u2 to enable the own echo canceller to adapt the coefficients. by the barker code the nt at the other end is enabled to synchronize. the detection of u2 is used by the nt as a criterion for synchronization. the m-channel on u may be used to transfer loop commands. u2a while the nt-rp is synchronizing on the received signal, the lt-rp sends out u2a to enable its echo canceller to adapt the coefficients, but sending no barker code it inhibits the nt to synchronize on the still asynchronous signal. due to proceeding synchronization, the u-frame may jump from time to time. u2a can not be detected in the nt at the far end. u1a u1a is similar to u1 but without framing information. while the nt synchronizes on the received signal, it sends out u1a to enable its echo canceller to adapt its coefficients, but sends no barker code to prevent the lt from synchronizing on the still asynchronous signal. due to proceeding synchronization, the u-frame may jump from time to time. u1a can not be detected by the far-end lt. u1 when synchronized, the nt sends the barker code and the lt may synchronize itself. u1 indicates additionally that a terminal equipment has not yet activated. upon receiving u1 the lt indicates the synchronized state by c/i ? uai ? to layer-2. usually during activation, no u1 signal is detected in the lt because the te is activated first and u1 changes to u3 before being detected. the m-channel on u may be used to transfer code error indications and 1 kbit/s transparent data. pef 82902 operational description data sheet 97 2001-11-09 u3 u3 indicates that the whole link to the te is synchronous in both directions. on detecting u3 the lt requests the nt by u4h to establish a fully transparent connection. the m-channel on u may be used to transfer code error indications and 1 kbit/s transparent data. u4h u4h requires the nt to go to the ? transparent ? state. on detecting u4h the nt stops sending signal u3 and informs the s-transceiver or a layer-2 device via the system interface. the m-channel on u may be used to transfer loop commands and 1 kbit/s transparent data. u4 u4 transports operational data on b and d channels. the m-channel on u may be used to transfer loop commands and 1 kbit/s transparent data. u5 u5 transports operational data on b and d channels. the m-channel on u may be used to transfer code error indications and 1 kbit/s transparent data. sp the t-sminti sends periodically single pulses once per millisecond on the u-interface. the test mode can be used for pulse mask measurements. lof loss of frame, generated by flywheel table 26 generation of the 4b3t signal elements upstream (nt to lt) downstream (lt to nt) symbols (ternary) sync word (tern ary) m sym bol (tern ary) binary data before scram bling u1w u2w resulting in a tone of: frequency: 7.5 khz duration: 2.13 ms when sending the wakeup tone is finished, signal awt is set and ternary "0" is sent 16 times + + + + + + + + ? ? ? ? ? ? ? ? n/a n/a n/a u1a u2a scrambled binary data 0 0 0 u1 u2 scrambled binary data yes yes 0 u3 scrambled binary data yes yes 1 table 25 4b3t signal elements (cont ? d) pef 82902 operational description data sheet 98 2001-11-09 table 27 s/t-interface signals u4h duration: 1 ms (warranted by state machine) yes yes 1 u5 u4 binary data from the digital interface yes yes bbd u0 u0 ternary continuous "0" 0 0 0 n/a sp sp single pulses once "+", 119 times "0" (repeatedl y) n/a n/a n/a signals from nt to te signals from te to nt info 0 no signal. info 0 no signal. info 1 a continuous signal with the following pattern: positive zero, negative zero, six ones. info 2 frame with all bits of b, d, and d-echo channels set to binary zero. bit a set to binary zero. n and l bits set according to the normal coding rules. info 3 synchronized frames with operational data on b and d-channels. info 4 frames with operational data on b, d, and d-echo channels. bit a set to binary one. table 26 generation of the 4b3t signal elements (cont ? d) pef 82902 operational description data sheet 99 2001-11-09 3.1.2 complete activation initiated by exchange figure 44 activation initiated by exchange note: the lt starts issuing signal u2 before the nt starts issuing u1a. this chronological order is not displayed for clarification. iom -2 te s/t-reference point nt u-reference point lt iom -2 dc info 0 dc u0 di info 0 di di actbylt_tsmint.vsd u0 u0 rsy ar ar u0 ar dc u1w u1a u2 u1 u2w info 2 ai u3 info 3 ar u4h u5 uai ai info 4 ai ar8/10 s 0 u k0 dfe-t sbcx-x or ipac-x u4 ai 1 ms c dc di ar ar ai ai uai pef 82902 operational description data sheet 100 2001-11-09 3.1.3 complete activation initiated by te figure 45 activation initiated by te note: the lt starts issuing signal u2 before the nt starts issuing u1a. this chronological order is not displayed for clarification. iom -2 te s/t-reference point nt u-reference point lt iom -2 dc info 0 dc u0 dc di info 0 di u0 di tim pu ar8/10 info 1 tim ar ar info 2 rsy info 0 info 3 ar ai ai info 4 ai u1w u0 u2w u0 u1a u2 actbyte_tsmint.vsd ar sbcx-x or ipac-x s 0 u k0 dfe-t rsy u1 u3 u4h u5 uai u4 ai 1 ms 8ms tim dc di ar ar ai ai uai pef 82902 operational description data sheet 101 2001-11-09 3.1.4 complete activation initiated by nt figure 46 activation initiated by nt note: the lt starts issuing signal u2 before the nt starts issuing u1a. this chronological order is not displayed for clarification. iom -2 te s/t-reference point nt u-reference point lt iom -2 dc info 0 dc u0 dc di info 0 di u0 di tim ar ar info 2 info 3 ar ai ai info 4 ai u1w u0 u2w u0 u1a u2 actbynt_tsmint.vsd ar sbcx-x or ipac-x s 0 u k0 dfe-t rsy u1 u3 u4h u5 uai u4 ai 1 ms dc di ar ai ai ar c ar 8/10 uai pef 82902 operational description data sheet 102 2001-11-09 3.1.5 complete deactivation figure 47 complete deactivation iom -2 te s/t-reference point nt u-reference point lt iom -2 ai info 4 ai u4 ar ar info 3 ai ai tim deac_tsmint.vsd dc u5 dr deac u0 u0 dr info 0 dc di dc di sbcx-x or ipac-x s 0 u k0 dfe-t info 0 di dr rsy dr ai ai dc di pef 82902 operational description data sheet 103 2001-11-09 3.1.6 loop 2 figure 48 loop 2 note: closing/resolving loop 2 may provoke the s-transceiver to resynchronize. in this case, the following c/i-codes are exchanged immediately on reception of ail/ai, respectively: du: ?rsy?, du: ?ai?, dd: ?ail?/?ai?. iom -2 te s/t-reference point nt u-reference point lt iom -2 ai info 4 u4 ar8/10 info 3 ai act_loop2_tsmint.vsd u5 ar ai ai 2b+d 2b+d 2b+d ail u4 (m-bit= 8x '+' ) ar2 ai u4 (m-bit= 8x '0' ) ar sbcx-x or ipac-x s 0 u k0 dfe-t ai ai ail ai pef 82902 operational description data sheet 104 2001-11-09 3.2 layer 1 loopbacks test loopbacks are specified by the national ptts in order to facilitate the location of defect systems. four different loopbacks are defined. the position of each loopback is illustrated in figure 49 . figure 49 test loopbacks loopbacks #1, #1a and #2 are controlled by the exchange. loopback #3 is controlled locally on the remote side. all four loopback types are transparent. this means all bits that are looped back will also be passed onwards in the normal manner. only the data looped back internally is processed; signals on the receive pins are ignored. the propagation delay of actually looped b and d channels data must be identical in all loopbacks. besides the remote controlled loopback stimulation via the m channel, the t-smint i features also direct loopback control via its register set. 3.2.1 analog loop-back s-transceiver the t-smint i provides test and diagnostic functions for the s/t interface: the internal local loop (internal loop a) is activated by a c/i command arl or by setting the bit lp_a (loop analog) in the s_cmd register if the layer-1 statemachine is disabled. the transmit data of the transmitter is looped back internally to the receiver. the data of the iom -2 input b- and d-channels are looped back to the output b- and d-channels. iom ? -2 pbx or te u-transceiver iom ? -2 iom ? -2 iom ? -2 u-transceiver u-transceiver u-transceiver u-transceiver u-transceiver loop 2 loop 3 loop 2 loop 1 a loop 2 loop 1 s-bus nt u u loop 2 repeater (optional) s-transceiver layer-1 controller layer-1 controller iom-2 exchange loop_2b1q.emf pef 82902 operational description data sheet 105 2001-11-09 the s/t interface level detector is enabled, i.e. if a level is detected this will be reported by the resynchronization indication (rsy) but the loop function is not affected. depending on the dis_tx bit in the s_conf2 register the internal local loop can be transparent or non transparent to the s/t line. the external local loop (external loop a) is activated in the same way as the internal local loop described above. additionally the exlp bit in the s_conf0 register has to be programmed and the loop has to be closed externally as described in figure 50 . the s/t interface level detector is disabled. figure 50 external loop at the s/t-interface 3.2.2 loopback no.2 for loopback #2 several alternatives exist. both the type of loopback and the location may vary. the following loopback types belong to the loopback-#2 category: complete loopback (b1,b2,d), in the u-transceiver complete loopback (b1,b2,d), in a downstream device b1-channel loopback, always performed in the u-transceiver b2-channel loopback, always performed in the u-transceiver all loop variations performed by the u-transceiver are closed as near to the internal iom -2 interface as possible. normally loopback #2 is controlled by the exchange. the maintenance channel is used for this purpose. scout-s(x) sx1 sx2 sr1 sr2 100 ? 100 ? pef 82902 operational description data sheet 106 2001-11-09 3.2.2.1 complete loopback when receiving the request for a complete loopback, the u transceiver passes it on to the downstream device, e.g. the s-bus transceiver. this is achieved by issuing the c/i- code ail in the ? transparent ? state or c/i = arl in states different than ? transparent ? figure 51 complete loopback options in nt-mode the complete loopback is either opened under control of the exchange via the maintenance channel or locally controlled via the c. no reset is required for loopback #2. the line stays active and is ready for data transmission. 3.2.2.2 loopback no.2 - single channel loopbacks single channel loopbacks are always performed directly in the u-transceiver. no difference between the b1-channel and the b2-channel loopback control procedure exists. 3.2.3 local loopbacks featured by the loop register besides the standardized remote loopbacks the u-transceiver features additional local loopbacks for enhanced test and debugging facilities. the local loopbacks that are featured by register loop are shown in figure 52 . they are closed in the u-transceiver itself and can be activated regardless of the current operational status. by the loop register it can be configured whether the loopback is closed only for the b1 and/or b2 or for 2b+d channels and whether the loopback is closed towards the internal iom -2 interface or towards the u-interface. by default the loopbacks are set to transparent mode. in transparent mode the data is both passed on and looped back. in non-transparent mode the data is not forwarded but substituted by 1s (idle code). 2b+d 2 b+d loop request u loop command l p2bymon8.vsd u-transceiver controller s-transceiver loop command pef 82902 operational description data sheet 107 2001-11-09 figure 52 loopbacks featured by register loop loopreg.emf loop.lb1=1 loop.lb2=1 loop.lbbd= 1 & loop.u/iom= 1 loop.lb1=1 loop.lb2=1 loop.lbbd= 1 & loop.u/iom= 0 iom-2 interface echo canceller + timing recovery bandgap, bias, refer. analog part line interface unit tx-fifo rx-fifo a g c equalizer pdm filter ? ? ? ? adc dac digital part u-transceiver u-de- framing de- scrambler scrambler 2b1q u- framing activation/ deactivation controller 2b1q pef 82902 operational description data sheet 108 2001-11-09 3.3 external circuitry 3.3.1 power supply blocking recommendation the following blocking circuitry is suggested. figure 53 power supply blocking 3.3.2 u-transceiver the t-sminti is connected to the twisted pair via a transformer. figure 54 shows the recommended external circuitry with external hybrid. the recommended protection circuitry is not displayed. vddd vddd vssd vssd vdda_sr vdda_ur vdda_ux vdda_sx vssa_ur vssa_ux vssa_sr vssa_sx 100nf 100nf 100nf 100nf 100nf 100nf gnd 3.3v 1f these capacitors should be located as near to the pins as possible 1) 1) 1) 1) 1) 1) 1) blocking_caps_smint.vsd pef 82902 operational description data sheet 109 2001-11-09 figure 54 external circuitry u-transceiver with external hybrid u-transformer parameters the following table lists parameters of typical u-transformers. table 28 u-transformer parameters u-transformer parameters symbol value unit u-transformer ratio; device side : line side n1 : 1.6 main inductanc of windings on the line side l h 7.5 mh leakage inductance of windings on the line side l s 120 h coupling capacitance between the windings on the device side and the windings on the line side c k 30 pf dc resistance of the windings on device side r b 0.9 ? dc resistance of the windings on line side r l 1.8 ? loop aout bout ain bin n c r t r4 r comp r comp >1 r3 r3 r4 r t extcirc_u_q2_exthybrid.emf pef 82902 operational description data sheet 110 2001-11-09 resistors of the external hybrid r3, r4 and r t r3 = 1.75 k ? r4 = 1.0 k ? r t = 25 ? resistors r comp / r t optional use of trafos with non negligible resistance r b , r l requires compensation resistors r comp depending on r b and r l : n 2 (2r comp + r b ) + r l = 20 ? (1) compliance with return loss measurements: n 2 (2r comp + 2r t + r out + r b ) + r l = 150 ? (2) r b , r l : see table 28 r out : see table 35 15nf capacitor to achieve optimum performance the 15nf capacitor should be mkt. a ceramic capacitor is not recommended. tolerances rs: 1% c = 15nf: 10-20% l h = 7.5mh: 10% 3.3.3 s-transceiver in order to comply to the physical requirements of itu recommendation i.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (emc), the s-transceiver needs some additional circuitry. pef 82902 operational description data sheet 111 2001-11-09 s-transformer parameters the following table 29 lists parameters of a typical s-transformer: table 29 s-transformer parameters transmitter the transmitter requires external resistors r stx = 47 ? in order to adjust the output voltage to the pulse mask (nominal 750 mv according to itu i.430, to be tested with the test mode ? tm1 ? ) on the one hand and in order to meet the output impedance of minimum 20 ? on the other hand (to be tested with the testmode ? continuous pulses ? ) on the other hand. note: the resistance of the s-transformer must be taken into account when dimensioning the external resistors r stx . if the transmit path contains additional components (e.g. a choke), then the resistance of these additional components must be taken into account, too. transformer parameters symbol value unit transformer ratio; device side : line side n2 : 1 main inductance of windings on the line side l h typ. 30 mh leakage inductance of windings on the line side l s typ. <3 h coupling capacitance between the windings on the device side and the windings on the line side c k typ. <100 pf dc resistance of the windings on device side r b typ. 2.4 ? dc resistance of the windings on line side r l typ. 1.4 ? pef 82902 operational description data sheet 112 2001-11-09 figure 55 external circuitry s-interface transmitter receiver the receiver of the s-transceiver is symmetrical. 10 k ? overall resistance are recommended in each receive path. it is preferable to split the resistance into two resistors for each line. this allows to place a high resistance between the transformer and the diode protection circuit (required to pass 96 khz input impedance test of itu i.430 [6] and ets 300012-1). the remaining resistance (1.8 k ? ) protects the s- transceiver itself from input current peaks. figure 56 external circuitry s-interface receiver 20...40 47 sx1 sx2 2 : 1 gnd v dd 47 dc point extcirc_s.vsd 1k8 1k8 sr1 sr2 2 : 1 gnd v dd 8k2 8k2 dc point extcirc_s.vsd pef 82902 operational description data sheet 113 2001-11-09 3.3.4 oscillator circuitry figure 57 illustrates the recommended oscillator circuit. figure 57 crystal oscillator table 30 crystal parameters external components and parasitics the load capacitance c l is computed from the external capacitances c ld , the parasitic capacitances c par (pin and pcb capacitances to ground and v dd ) and the stray capacitance c io between xin and xout: for a specific crystal the total load capacitance is predefined, so the equation must be solved for the external capacitances c ld , which is usually the only variable to be determined by the circuit designer. typical values for the capacitances c ld connected to the crystal are 22 - 33 pf. 3.3.5 general ? low power leds parameter symbol limit values unit frequency f 15.36 mhz frequency calibration tolerance +/-60 ppm load capacitance c l 20 pf max. resonance resistance r1 20 ? max. shunt capacitance c 0 7pf oscillator mode fundamental 15.36 mhz xout xin c ld c ld c l c ld c par + () c ld c par + () c ld c par + () c ld c par + () + ------------------------------------------------------------------------ c io + = pef 82902 register description data sheet 114 2001-11-09 4 register description 4.1 address space figure 58 address space 4.2 interrupts special events in the t-smint i are indicated by means of a single interrupt output, which requests the host to read status information from the t-smint i or transfer data from/to the t-smint i. since only one int request output is provided, the cause of an interrupt must be determined by the host reading the interrupt status registers of the t-smint i. the structure of the interrupt status registers is shown in figure 59 . iom -2 handler interrupt, global registers 30 h 40 h 60 h (cda, tsdp, cr, sti) u-transceiver 7d h s-transceiver 3c h monitor handler 5c h ci-register 00 h 2e h modeh-register reserved 22 h pef 82902 register description data sheet 115 2001-11-09 figure 59 t-smint i interrupt status registers after the t-smint i has requested an interrupt by setting its int pin to low, the host must read first the t-smint i interrupt status register (ista) in the associated interrupt service routine. the int pin of the t-smint i remains active until all interrupt sources are cleared. therefore, it is possible that the int pin is still active when the interrupt service routine is finished. each interrupt indication of the interrupt status registers can selectively be masked by setting the respective bit in the mask register. for some interrupt controllers or hosts it might be necessary to generate a new edge on the interrupt line to recognize pending interrupts. this can be done by masking all interrupts at the end of the interrupt service routine (writing ff h into the mask register) and writing back the old mask to the mask register. 0 1 1 cic st mos s wov int sti11 ista mask sqc msti sti sti10 sti20 sti21 stov10 stov11 stov20 stov21 cic1 ci1e cic0 cir0 istas cix1 ric sqc ric masks ld ld cic st mos s wov mre mdr mie mda mer mab mosr mocr sti11 sti10 sti20 sti21 stov10 stov11 stov20 stov21 sqw sqw ack11 ack10 ack20 ack21 asti uu istau masku ci rds 1 1 1 1ms ci rds 0 0 0 0 1ms 0 1 1 0 pef 82902 register description data sheet 116 2001-11-09 4.3 register summary r(0) = reserved, implemented as zero ci handler name 7 6 5 4 3 2 1 0 addr r/w res reserved 00 h -21 h modeh 1 1 0 r(0) 0 dim2 dim1 dim0 22 h r/w c0 h reserved 23 h - 2d h cir0 codr0 cic0 cic1 s/g bas 2e h rf3 h cix0 codx0 tba2 tba1 tba0 bac 2e h wfe h cir1 codr1 cicw ci1e 2f h rfe h cix1 codx1 cicw ci1e 2f h wfe h pef 82902 register description data sheet 117 2001-11-09 s-transceiver name76543210addrr/wres s_ conf0 dis_ tr bus en_ icv 0 l1sw 0 exlp 0 30 h r/w 40 h reserved 31 h s_ conf2 dis_ tx 000000032 h r/w 80 h s_sta rinf 0 icv 0 fsyn 0 ld 33 h r00 h s_cmd xinf dprio 1 pd lp_a 0 34 h r/w 08 h sqrr msyn mfen 0 0 sqr1 sqr2 sqr3 sqr4 35 h r00 h sqxr 0 mfen 0 0 sqx1 sqx2 sqx3 sqx4 35 h w00 h reserved 36 h -37 h istas 0 x x x ld ric sqc sqw 38 h r00 h masks 1111ldricsqcsqw39 h r/w ff h s_ mode 0000dch_ inh mode2-0 3a h r/w 02 h reserved 3b h pef 82902 register description data sheet 118 2001-11-09 interrupt, general configuration name 7 6 5 4 3 2 1 0 addr r/w res ista u st cic 0 wov s mos 0 3c h r00 h mask u st cic 1 wov s mos 1 3c h wff h mode1 mclk cds wtc1 wtc2 cfs rss2 rss1 3d h r/w 04 h mode2 led2 led1 ledc 0 0 amod ppsdx 3e h r/w 00 h id 0 0 design 3f h r20 h sres 0 0 res_ ci/tic 0 0 0 res_ s res_ u 3f h w00 h pef 82902 register description data sheet 119 2001-11-09 iom handler (timeslot, data port selection, cda data and cda control register) name 76543210addrr/wres cda10 controller data access register 40 h r/w ff h cda11 controller data access register 41 h r/w ff h cda20 controller data access register 42 h r/w ff h cda21 controller data access register 43 h r/w ff h cda_ tsdp10 dps 0 0 0tss44 h r/w 00 h cda_ tsdp11 dps 0 0 0tss45 h r/w 01 h cda_ tsdp20 dps 0 0 0tss46 h r/w 80 h cda_ tsdp21 dps 0 0 0tss47 h r/w 81 h reserved 48 h - 4b h s_ tsdp_ b1 dps 0 0 0tss4c h r/w 84 h s_ tsdp_ b2 dps 0 0 0tss4d h r/w 85 h cda1_ cr 0 0en_ tbm en_i1 en_i0 en_o1 en_o0 swap 4e h r/w 00 h cda2_ cr 0 0en_ tbm en_i1 en_i0 en_o1 en_o0 swap 4f h r/w 00 h pef 82902 register description data sheet 120 2001-11-09 iom handler (control registers, synchronous transfer interrupt control) name 7 6 5 4 3 2 1 0 addr r/w res reserved 50 h s_cr 1 ci_cs en_ d en_ b2r en_ b1r en_ b2x en_ b1x d_cs 51 h r/w ff h ci_cr dps_ ci1 en_ ci1 0 001 0 52 h r/w 04 h mon_ cr dps en_ mon 0 000 mcs 53 h r/w 40 h sds1_ cr ens_ tss ens_ tss+1 ens_ tss+3 0tss54 h r/w 00 h sds2_ cr ens_ tss ens_ tss+1 ens_ tss+3 0tss55 h r/w 00 h iom_cr spu 0 0 tic_ dis en_ bcl 0dis_ od dis_ iom 56 h r/w 08 h mcda mcda21 mcda20 mcda11 mcda10 57 h rff h sti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 58 h r00 h asti 0000ack 21 ack 20 ack 11 ack 10 58 h w00 h msti stov 21 stov 20 stov 11 stov 10 sti 21 sti 20 sti 11 sti 10 59 h r/w ff h reserved 5a h - 5b h pef 82902 register description data sheet 121 2001-11-09 monitor handler name 7 6 5 4 3 2 1 0 addr r/w res mor monitor receive data 5c h rff h mox monitor transmit data 5c h wff h mosr mdr mer mda mab 0 0 0 0 5d h r00 h mocr mre mrc mie mxc 0 0 0 0 5e h r/w 00 h msta 00000mac0tout5f h r00 h mconf0000000tout5f h w00 h pef 82902 register description data sheet 122 2001-11-09 note: registers, which are denoted as ?reserved?, may not be accessed by the c, neither for read nor for write operations. 4.3.1 reset of u-transceiver functions during deactivation or with c/i-code reset the following u-transceiver register is reset upon transition to state ? deactivating ? or with software reset: u-transceiver name 76543210addrr/wres opmode 0 uci 0 0 0 0 0 060 h r*/w 00 h reserved 61 h - 6c h ucir 0 0 0 0 c/i code output 6d h r00 h uciw 0 0 0 0 c/i code input 6e h w01 h reserved 6f h loop 0 0 trans u/iom 1 lbbd lb2 lb1 70 h r*/w 08 h reserved 71 h rds block error counter value 72 h r00 h reserved 73 h - 79 h istau 0 ci rds 0 0 0 0 1 ms 7a h r00 h masku 1 ci rds 1 1 1 1 1 ms 7b h r*/w ff h reserved 7c h fw_ version fw version number 7d h r3e h pef 82902 register description data sheet 123 2001-11-09 4.3.2 mode register evaluation timing table 32 lists registers, which are evaluated and executed immediately. table 31 reset of u-transceiver functions during deactivation or with c/i- code reset register affected bits/ comment loop only the bits lbbd, lb2 and lb1 are reset table 32 mode register with immediate evaluation and execution register affected bits comment opmode uci loop complete register masku complete register pef 82902 register description data sheet 124 2001-11-09 4.4 detailed c/i registers 4.4.1 modeh - mode register iom-2 modeh read/write address: 22 h value after reset: c0 h 4.4.2 cir0 - command/indication receive 0 cir0 read address: 2e h value after reset: f3 h 70 1 1 0 r(0) 0 dim2 dim1 dim0 dim2-0 digital interface modes these bits define the characteristics of the iom data ports (du, dd). the dim0 bit enables/disables the stop/go bit (s/g) evaluation. the dim1 bit enables/disables the tic bus access. the effect of the individual dim bits is as follows: 0-0 = stop/go bit evaluation is disabled 0-1 = stop/go bit evaluation is enabled 00- = tic bus access is enabled 01- = tic bus access is disabled 1xx = reserved 70 codr0 cic0 cic1 s/g bas pef 82902 register description data sheet 125 2001-11-09 note: the codr0 bits are updated every time a new c/i-code is detected in two consecutive iom-frames. if several consecutive valid new codes are detected and cir0 is not read, only the first and the last c/i code are made available in cir0 at the first and second read of that register. codr0 c/i0 code receive value of the received command/indication code. a c/i-code is loaded in codr0 only after being the same in two consecutive iom-frames and the previous code has been read from cir0. cic0 c/i0 code change 0 = no change in the received command/indication code has been recognized 1 = a change in the received command/indication code has been recognized. this bit is set only when a new code is detected in two consecutive iom-frames. it is reset by a read of cir0. cic1 c/i1 code change 0 = no change in the received command/indication code has been recognized 1 = a change in the received command/indication code in iom-channel 1 has been recognized. this bit is set when a new code is detected in one iom-frame. it is reset by a read of cir0. s/g stop/go bit monitoring indicates the availability of the upstream d-channel; 0 = go 1 = stop bas bus access status indicates the state of the tic-bus: 0 = the t-smint i itself occupies the d- and c/i-channel 1 = another device occupies the d- and c/i-channel pef 82902 register description data sheet 126 2001-11-09 4.4.3 cix0 - command/indication transmit 0 cix0 write address: 2e h value after reset: fe h 4.4.4 cir1 - command/indication receive 1 cir1 read address: 2f h value after reset: fe h 70 codx0 tba2 tba1 tba0 bac codx0 c/i0-code transmit code to be transmitted in the c/i-channel 0. the code is only transmitted if the tic bus is occupied, otherwise ? 1s ? are transmitted. tba2-0 tic bus address defines the individual address for the t-smint i on the iom bus. this address is used to access the c/i- and d-channel on the iom interface. note: if only one device is liable to transmit in the c/i- and d-channels of the iom it should always be given the address value ? 7 ? . bac bus access control only valid if the tic-bus feature is enabled (mode:dim2-0). 0 = inactive 1 = the t-smint i will try to access the tic-bus to occupy the c/i- channel even if no d-channel frame has to be transmitted. it should be reset when the access has been completed to grant a similar access to other devices transmitting in that iom-channel. note: access is always granted by default to the t-smint i with tic-bus address (tba2-0, cix0 register) ? 7 ? , which has the lowest priority in a bus configuration. pef 82902 register description data sheet 127 2001-11-09 4.4.5 cix1 - command/indication transmit 1 cix1 write address: 2f h value after reset: fe h 70 codr1 cicw ci1e codr1 c/i1-code receive cicw c/i-channel width contains the read back value from cix1 register (see below) 0 = 4 bit c/i1 channel width 1 = 6 bit c/i1 channel width ci1e c/i1-channel interrupt enable contains the read back value from cix1 register (see below) 0 = interrupt generation ista.cic of cir0.cic1is masked 1 = interrupt generation ista.cic of cir0.cic1 is enabled 70 codx1 cicw ci1e codx1 c/i1-code transmit bits 5-0 of c/i-channel 1 cicw c/i-channel width 0 = 4 bit c/i1 channel width 1 = 6 bit c/i1 channel width pef 82902 register description data sheet 128 2001-11-09 4.5 detailed s-transceiver registers 4.5.1 s_conf0 - s-transceiver configuration register 0 s_ conf0 read/write address: 30 h value after reset: 40 h the c/i1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. however, in write direction the full codx1 code is transmitted, i.e. the host must write the higher two bits to ? 1 ? . ci1e c/i1-channel interrupt enable 0 = interrupt generation ista.cic of cir0.cic1is masked 1 = interrupt generation ista.cic of cir0.cic1 is enabled 70 dis_tr bus en_ icv 0 l1sw 0 exlp 0 dis_tr disable transceiver 0 = all s-transceiver functions are enabled. 1 = all s-transceiver functions are disabled and powered down (analog and digital parts). bus point-to-point / bus selection 0 = adaptive timing (point-to-point, extended passive bus). 1 = fixed timing (short passive bus), directly derived from transmit clock. en_icv enable far end code violation 0 = normal operation. 1 = icv enabled. the receipt of at least one illegal code violation within one multi-frame according to ansi t1.605 is indicated by the c/i indication ? 1011 ? (cvr) in two consecutive iom frames. pef 82902 register description data sheet 129 2001-11-09 4.5.2 s_conf2 - s-transmitter configuration register 2 s_ conf2 read/write address: 32 h value after reset: 80 h 4.5.3 s_sta - s-transceiver status register s_ sta read address: 33 h value after reset: 00 h l1sw enable layer 1 state machine in software 0 = layer 1 state machine of the t-smint i is used. 1 = layer 1 state machine is disabled. the functionality must be realized in software. the commands are written to register s_cmd and the status read in the s_sta. exlp external loop in case the analog loopback is activated with c/i = arl or with the lp_a bit in the s_cmd register the loop is a 0 = internal loop next to the line pins 1 = external loop which has to be closed between sr1/sr2 and sx1/ sx2 note: for the external loop the transmitter must be enabled (s_conf2:dis_tx = 0). 70 dis_tx0000000 dis_tx disable line driver 0 = transmitter is enabled 1 = transmitter is disabled pef 82902 register description data sheet 130 2001-11-09 important: this register is used only if the layer 1 state machine of the device is disabled (s_conf0:l1sw = 1) and implemented in software! with the layer 1 state machine enabled, the signals from this register are automatically evaluated. 4.5.4 s_cmd - s-transceiver command register s_ cmd read/write address: 34 h value after reset: 08 h 70 rinf 0 icv 0 fsyn 0 ld rinf receiver info 00 = received info 0 (no signal) 01 = received any signal except info 0 or info 3 10 = reserved 11 = received info 3 icv illegal code violation 0 = no illegal code violation is detected. 1 = illegal code violation (ansi t1.605) in data stream is detected. fsyn frame synchronization state 0 = the s/t receiver is not synchronized. 1 = the s/t receiver has synchronized to the framing bit f. ld level detection 0 = no receive signal has been detected on the line. 1 = any receive signal has been detected on the line. 70 xinf dprio 1 pd lp_a 0 pef 82902 register description data sheet 131 2001-11-09 important: this register - except bit dprio - is writable only if the layer 1 state machine of the device is disabled (s_conf0.l1sw = 1) and implemented in software! with the device layer 1 state machine enabled, the signals from this register are automatically generated. dprio can also be written in intelligent nt mode. 4.5.5 sqrr - s/q-channel receive register sqrr read address: 35 h value after reset: 00 h xinf transmit info 000 = transmit info 0 001 = reserved 010 = transmit info 2 011 = transmit info 4 100 = send continuous pulses at 192 kbit/s alternating or 96 khz rectangular, respectively (tm2) 101 = send single pulses at 4 kbit/s with alternating polarity corresponding to 2 khz fundamental mode (tm1) 11x = reserved dprio d-channel priority 0 = priority class 1 for d channel access on iom 1 = priority class 2 for d channel access on iom pd power down 0 = the transceiver is set to operational mode 1 = the transceiver is set to power down mode lp_a loop analog the setting of this bit corresponds to the c/i command arl. 0 = analog loop is open 1 = analog loop is closed internally or externally according to the exlp bit in the s_conf0 register pef 82902 register description data sheet 132 2001-11-09 4.5.6 sqxr- s/q-channel transmit register sqxr write address: 35 h value after reset: 00 h 70 msyn mfen 0 0 sqr1 sqr2 sqr3 sqr4 msyn multi-frame synchronization state 0 = the s/t receiver has not synchronized to the received f a and m bits 1 = the s/t receiver has synchronized to the received f a and m bits mfen multiframe enable read-back of the mfen bit of the sqxr register 0 = s/t multiframe is disabled 1 = s/t multiframe is enabled sqr1-4 received s/q bits received q bits in frames 1, 6, 11 and 16 70 0 mfen 0 0 sqx1sqx2sqx3sqx4 mfen multiframe enable used to enable or disable the multiframe structure. 0 = s/t multiframe is disabled 1 = s/t multiframe is enabled sqx1-4 transmitted s/q bits transmitted s bits in frames 1, 6, 11 and 16 pef 82902 register description data sheet 133 2001-11-09 4.5.7 istas - interrupt status register s-transceiver istas read address: 38 h value after reset: 00 h 70 x x x x ld ric sqc sqw these bits are set if an interrupt status occurs and an interrupt signal is activated if the corresponding mask bit is set to ? 0 ? . if the mask bit is set to ? 1 ? no interrupt is generated, however the interrupt status bit is set in istas. ric, sqc and sqw are cleared by reading the corresponding source register s_sta, sqrr or writing sqxr, respectively. x reserved ld level detection 0 = inactive 1 = any receive signal has been detected on the line. this bit is set to ? 1 ? (i.e. an interrupt is generated if not masked) as long as any receive signal is detected on the line. ric receiver info change 0 = inactive 1 = ric is activated if one of the s_sta bits rinf or icv has changed. sqc s/q-channel change 0 = inactive 1 = a change in the received 4-bit q-channel has been detected. the new code can be read from the sqrx bits of registers sqrr within the next multiframe 1) . this bit is reset by a read access to the sqrr register. sqw s/q-channel writable pef 82902 register description data sheet 134 2001-11-09 4.5.8 masks - mask s-transceiver interrupt masks read/write address: 39 h value after reset: ff h 4.5.9 s_mode - s-transceiver mode s_ mode read/write address: 3a h value after reset: 02 h 0 = inactive 1 = the s channel data for the next multiframe is writable. the register for the s bits to be transmitted has to be written within the next multiframe. this bit is reset by writing register sqxr. this timing signal is indicated with the start of every multiframe. data which is written right after sqw-indication will be transmitted with the start of the following multiframe. data which is written before sqw-indication is transmitted in the multiframe which is indicated by sqw. sqw and sqc could be generated at the same time. 1) register sqrr stays valid as long as no code change has been received. 70 1111ldricsqcsqw bit 3..0 mask bits 0 = the transceiver interrupts ld, ric, sqc and sqw are enabled 1 = the transceiver interrupts ld, ric, sqc and sqw are masked 70 0000dch_inh mode pef 82902 register description data sheet 135 2001-11-09 4.6 interrupt and general configuration registers 4.6.1 ista - interrupt status register ista read address: 3c h value after reset: 00 h dch_ inh d-channel inhibit 0 = inactive 1 = the s-transceiver blocks the access to the d-channel on s by inverting the e-bits. mode mode selection 000 = reserved 001 = reserved 010 = nt (without d-channel handler) 011 = lt-s (without d-channel handler) 110 intelligent nt mode (with nt state machine and with d-channel handler) 111 intelligent nt mode (with lt-s state machine and with d-channel handler) 100 reserved 101 reserved 70 u st cic 0 wov s mos 0 u u-transceiver interrupt 0 = inactive 1 = an interrupt was generated by the u-transceiver. read the istau register. pef 82902 register description data sheet 136 2001-11-09 note: a read of the ista register clears only the wov interrupt. the other interrupts are cleared by reading the corresponding status register. 4.6.2 mask - mask register mask write address: 3c h value after reset: ff h st synchronous transfer 0 = inactive 1 = this interrupt enables the microcontroller to lock on to the iom ? -2 timing, for synchronous transfers. cic c/i channel change 0 = inactive 1 = a change in c/i0 channel or c/i1 channel has been recognized. the actual value can be read from cir0 or cir1. 0 = inactive wov watchdog timer overflow 0 = inactive 1 = signals the expiration of the watchdog timer, which means that the microcontroller has failed to set the watchdog timer control bits wtc1 and wtc2 (mode1 register) in the correct manner. a reset out pulse on pin rsto has been generated by the t-smint i. s s-transceiver interrupt 0 = inactive 1 = an interrupt was generated by the s-transceiver. read the istas register. mos monitor status 0 = inactive 1 = a change in the monitor status register (mosr) has occurred. 0 = inactive pef 82902 register description data sheet 137 2001-11-09 each interrupt source in the ista register can be selectively masked by setting the corresponding bit in mask to ? 1 ? . masked interrupt status bits are not indicated when ista is read. instead, they remain internally stored and pending, until the mask bit is reset to ? 0 ? . note: in the event of a c/i channel change, cic is set in ista even if the corresponding mask bit in mask is active, but no interrupt is generated. 4.6.3 mode1 - mode1 register mode1 read/write address: 3d h value after reset: 04 h 70 u st cic 1 wov s mos 1 bit 7..0 mask bits 0 = interrupt is not masked 1 = interrupt is masked 70 mclk cds wtc1 wtc2 cfs rss2 rss1 mclk master clock frequency the master clock frequency bits control the microcontroller clock output depending on mode1.cds = ? 0 ? or ? 1 ? (table table 2.1.3 ). mode1.cds = ? 0 ? mode1.cds = ? 1 ? 00 = 3.84 mhz 7.68 mhz 01 = 0.96 mhz 1.92 mhz 10 = 7.68 mhz 15.36 mhz 11 = disabled disabled pef 82902 register description data sheet 138 2001-11-09 cds clock divider selection 0 = the 15.36 mhz oscillator clock divided by two is input to the mclk prescaler 1 = the 15.36 mhz oscillator clock is input to the mclk prescaler. wtc1, 2 watchdog timer control 1, 2 after the watchdog timer mode has been selected (rss = ? 11 ? ) the watchdog timer is started. during every time period of 128 ms the microcontroller has to program the wtc1 and wtc2 bit in the following sequence ( chapter 2.2 ): 10 first step 01 second step to reset and restart the watchdog timer. if not, the timer expires and a wov-interrupt (ista register) together with a reset out pulse on pin rsto is generated. the watchdog timer runs only when the internal iom ? -2 clocks are active, i.e. the watchdog timer is dead when bit cfs = 1 and the u and s- transceivers are in state power down. cfs configuration select 0 = the iom ? -2 interface clock and frame signals are always active, ? deactivated state ? of the u-transceiver and the s-transceiver included. 1 = the iom ? -2 interface clocks and frame signals are inactive in the ? deactivated state ? of the u-transceiver and the s-transceiver. rss2, rss1 reset source selection 2,1 the t-smint i reset sources can be selected according to the table below. c/i code change watchdog timer por/uvd and rst 00 =----x 01 = rsto disabled (high impedance) 10 = x -- x 11 = -- x x pef 82902 register description data sheet 139 2001-11-09 4.6.4 mode2 - mode2 register mode2 read/write address: 3e h value after reset: 00 h 4.6.5 id - identification register id read address: 3f h value after reset: 20 h 70 led2 led1 ledc 0 0 0 amod ppsdx led2,1 led control on pin act 00 = high 01 = flashing at 2 hz (1 : 1)* 10 = flashing at 1 hz (3 : 1)* 11 = low ledc led control enable 0 = led is controlled by the state machines as defined in table 3 . 1 = led is controlled via bits led2,1. amod address mode selects between direct and indirect register access of the parallel microcontroller interface. 0 = indirect address mode is selected. the address line a0 is used to select between address (a0 = ? 0 ? ) and data (a0 = ? 1 ? ) register 1 = direct address mode is selected. the address is applied to the address bus (a0-a6) ppsdx push/pull output for sdx 0 = the sdx pin has open drain characteristic 1 = the sdx pin has push/pull characteristic pef 82902 register description data sheet 140 2001-11-09 4.6.6 sres - software reset register sres write address: 3f h value after reset: 00 h 4.7 detailed iom ? -2 handler registers 4.7.1 cdaxy - controller data access register xy these registers are used for microcontroller access to the iom ? -2 timeslots as well as for timeslot manipulations. (e.g. loops, shifts, ... see also ?controller data access (cda)? on page 30 ). 70 0 0 design design design number the design number (design) allows to identify different hardware designs 1) of the t-smint i by software. 100000: version 1.1 1) distinction of different firmware versions is also possible by readingregister (7d) h in the address space of the u-transceiver (see chapter 4.9.8 ). 70 0 0 res_ ci/tic 0 0 0 res_s res_u res_xx reset_xx 0 = deactivates the reset of the functional block xx 1 = activates the reset of the functional block xx. the reset state is activated as long as the bit is set to ? 1 ? pef 82902 register description data sheet 141 2001-11-09 cdaxy read/write address: 40-43 h data register cdaxy which can be accessed by the controller. 4.7.2 xxx_tsdpxy - time slot and data port selection for chxy xxx_tsdpxy read/write address: 44-4d h this register determines the time slots and the data ports on the iom ? -2 interface for the data channels xy of the functional units xxx (controller data access (cda) and s- transceiver (s)). note: the u-transceiver is always in iom-2 channel 0. 70 controller data access register register value after reset register address cda10 ff h 40 h cda11 ff h 41 h cda20 ff h 42 h cda21 ff h 43 h 70 dps 0 0 0 tss register value after reset register address cda_tsdp10 00 h (= output on b1-dd) 44 h cda_tsdp11 01 h (= output on b2-dd) 45 h cda_tsdp20 80 h (= output on b1-du) 46 h cda_tsdp21 81 h (= output on b2-du) 47 h reserved 48-4b h s_tsdp_b1 84 h (= output on ts4-du) 4c h s_tsdp_b2 85 h (= output on ts5-du) 4d h pef 82902 register description data sheet 142 2001-11-09 4.7.3 cdax_cr - control register controller data access ch1x cdax_cr read/write address: 4e-4f h dps data port selection 0 = the data channel xy of the functional unit xxx is output on dd. the data channel xy of the functional unit xxx is input from du. 1 = the data channel xy of the functional unit xxx is output on du. the data channel xy of the functional unit xxx is input from dd. note: for the cda (controller data access) data the input is determined by the cdax_cr.swap bit. if swap = ? 0 ? the input for the cdaxy data is vice versa to the output setting for cdaxy. if the swap = ? 1 ? the input from cdax0 is vice versa to the output setting of cdax1 and the input from cdax1 is vice versa to the output setting of cdax0. tss timeslot selection selects one of the 12 timeslots from 0...11 on the iom ? -2 interface for the data channels. 70 0 0 en_tbm en_i1 en_i0 en_o1 en_o0 swap register value after reset register address cda1_cr 00 h 4e h cda2_cr 00 h 4f h en_tbm enable tic bus monitoring 0 = the tic bus monitoring is disabled 1 = the tic bus monitoring with the cdax0 register is enabled. the tsdpx0 register must be set to 08 h for monitoring from du, or 88 h for monitoring from dd. en_i1, en_i0 enable input cdax1, cdax0 pef 82902 register description data sheet 143 2001-11-09 4.7.4 s_cr - control register s-transceiver data s_cr read/write address: 51 h value after reset: ff h 0 = the input of the cdax1, cdax0 register is disabled 1 = the input of the cdax1, cdax0 register is enabled en_o1, en_o0 enable output cdax1, cdax0 0 = the output of the cdax1, cdax0 register is disabled 1 = the output of the cdax1, cdax0 register is enabled swap swap inputs 0 = the time slot and data port for the input of the cdaxy register is defined by its own tsdpxy register. the data port for the cdaxy input is vice versa to the output setting for cdaxy. 1 = the input (time slot and data port) of the cdax0 is defined by the tsdp register of cdax1 and the input of cdax1 is defined by the tsdp register of cdax0. the data port for the cdax0 input is vice versa to the output setting for cdax1. the data port for the cdax1 input is vice versa to the output setting for cdax0. the input definition for time slot and data port cdax0 are thus swapped to cdax1 and for cdax1 to cdax0. the outputs are not affected by the swap bit. 70 1 ci_cs en_d en_b2r en_b1r en_b2x en_b1x d_cs ci_cs c/i channel selection this bit is used to select the iom channel to which the s-transceiver c/i- channel is related to. 0 = c/i-channel in iom-channel 0 1 = c/i-channel in iom-channel 1 pef 82902 register description data sheet 144 2001-11-09 4.7.5 ci_cr - control register for ci1 data ci_cr read/write address: 52 h value after reset: 04 h en_d enable transceiver d-channel data 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. en_b2r enable transceiver b2 receive data (transmitter receives from iom) 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. en_b1r enable transceiver b1 receive data (transmitter receives from iom) 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. en_b2x enable transceiver b2 transmit data (transmitter transmits to iom) 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. en_b1x enable transceiver b1 transmit data (transmitter transmits to iom) 0 = the corresponding data path to the transceiver is disabled 1 = the corresponding data path to the transceiver is enabled. these bits are used to individually enable/disable the d-channel and the receive/transmit paths for the b-channels for the s-transceiver. d_cs d channel selection this bit is used to select the iom channel to which the s-transceiver d- channel is related to. 0 = d-channel in iom-channel 0 1 = d-channel in iom-channel 1 pef 82902 register description data sheet 145 2001-11-09 4.7.6 mon_cr - control register monitor data mon_cr read/write address: 53 h value after reset: 40 h 70 dps_ci1 en_ci1 0 0 0 1 0 dps_ci1 data port selection ci1 handler 0 = the ci1 data is output on dd and input from du 1 = the ci1 data is output on du and input from dd en_ci1 enable ci1 handler 0 = ci1 data access is disabled 1 = ci1 data access is enabled note: the timeslot for the c/i1 handler cannot be programmed but is fixed to iom channel 1. 70 dps en_mon 0 0 0 0 mcs dps data port selection 0 = the monitor data is output on dd and input from du 1 = the monitor data is output on du and input from dd en_mon enable output 0 = the monitor data input and output is disabled 1 = the monitor data input and output is enabled mcs monitor channel selection 00 = the monitor data is output on mon0 pef 82902 register description data sheet 146 2001-11-09 4.7.7 sds1_cr - control register serial data strobe 1 sds1_cr read/write address: 54 h value after reset: 00 h this register is used to select position and length of the strobe signal 1. the length can be any combination of two 8-bit timeslot (ens_tss, ens_tss+1) and one 2-bit timeslot (ens_tss+3). 01 = the monitor data is output on mon1 10 = the monitor data is output on mon2 11 = not defined 70 ens_ tss ens_ tss+1 ens_ tss+3 0tss ens_ tss enable serial data strobe of timeslot tss 0 = the serial data strobe signal sds1 is inactive during tss 1 = the serial data strobe signal sds1 is active during tss ens_ tss+1 enable serial data strobe of timeslot tss+1 0 = the serial data strobe signal sds1 is inactive during tss+1 1 = the serial data strobe signal sds1 is active during tss+1 ens_ tss+3 enable serial data strobe of timeslot tss+3 (d-channel) 0 = the serial data strobe signal sds1 is inactive during the d-channel (bit7, 6) of tss+3 1 = the serial data strobe signal sds1 is active during the d-channel (bit7, 6) of tss+3 pef 82902 register description data sheet 147 2001-11-09 4.7.8 sds2_cr - control register serial data strobe 2 sds2_cr read/write address: 55 h value after reset: 00 h this register is used to select position and length of the strobe signal 2. the length can be any combination of two 8-bit timeslot (ens_tss, ens_tss+1) and one 2-bit timeslot (ens_tss+3). tss timeslot selection selects one of 12 timeslots on the iom ? -2 interface (with respect to fsc) during which sds1 is active high. the data strobe signal allows standard data devices to access a programmable channel. 70 ens_ tss ens_ tss+1 ens_ tss+3 0tss ens_ tss enable serial data strobe of timeslot tss 0 = the serial data strobe signal sds2 is inactive during tss 1 = the serial data strobe signal sds2 is active during tss ens_ tss+1 enable serial data strobe of timeslot tss+1 0 = the serial data strobe signal sds2 is inactive during tss+1 1 = the serial data strobe signal sds2 is active during tss+1 ens_ tss+3 enable serial data strobe of timeslot tss+3 (d-channel) 0 = the serial data strobe signal sds2 is inactive during the d-channel (bit7, 6) of tss+3 1 = the serial data strobe signal sds2 is active during the d-channel (bit7, 6) of tss+3 pef 82902 register description data sheet 148 2001-11-09 4.7.9 iom_cr - control register iom data iom_cr read/write address: 56 h value after reset: 08 h tss timeslot selection selects one of 12 timeslots on the iom ? -2 interface (with respect to fsc) during which sds2 is active high. the data strobe signal allows standard data devices to access a programmable channel. 70 spu 0 0 tic_dis en_bcl 0 dis_od dis_iom spu software power up 0 = the du line is normally used for transmitting data. 1 = setting this bit to ? 1 ? will pull the du line to low. this will enforce the t-smint i and other connected layer 1 devices to deliver iom- clocking. tic_dis tic bus disable 0 = the last octet of the last iom time slot (ts 11) is used as tic bus. 1 = the tic bus is disabled. the last octet of the last iom time slot (ts 11) can be used like any other time slot. this means that the timeslots tic, a/b, s/g and bac are not available any more. en_bcl enable bit clock bcl 0 = the bcl clock is disabled (output is high impedant) 1 = the bcl clock is enabled dis_od disable open drain 0 = iom outputs are open drain driver 1 = iom outputs are push pull driver pef 82902 register description data sheet 149 2001-11-09 4.7.10 mcda - monitoring cda bits mcda read address: 57 h value after reset: ff h 4.7.11 sti - synchronous transfer interrupt sti read address: 58 h value after reset: 00 h dis_iom disable iom dis_iom should be set to ? 1 ? if external devices connected to the iom interface should be ? disconnected ? e.g. for power saving purposes. however, the t-smint i internal operation is independent of the dis_iom bit. 0 = the iom interface is enabled 1 = the iom interface is disabled (fsc, dcl, clock outputs have high impedance; du, dd data line inputs are switched off and outputs are high impedant) 70 mcda21 mcda20 mcda11 mcda10 bit7 bit6 bit7 bit6 bit7 bit6 bit7 bit6 mcdaxy monitoring cdaxy bits bit 7 and bit 6 of the cdaxy registers are mapped into the mcda register. this can be used for monitoring the d-channel bits on du and dd and the ? echo bits ? on the tic bus with the same register. 70 stov21 stov20 stov11 stov10 sti21 sti20 sti11 sti10 pef 82902 register description data sheet 150 2001-11-09 note: st0vxy and ackxy are useful for synchronizing microcontroller accesses and receive/transmit operations. one bcl clock is equivalent to two dcl clocks. 4.7.12 asti - acknowledge synchronous transfer interrupt asti write address: 58 h value after reset: 00 h for all interrupts in the sti register the following logical states are applied 0 = interrupt has not occurred 1 = interrupt has occurred stovxy synchronous transfer overflow interrupt enabled stov interrupts for a certain stixy interrupt are generated when the stixy has not been acknowledged in time via the ackxy bit in the asti register. this must be one (for dps = ? 0 ? ) or zero (for dps = ? 1 ? ) bcl clock cycles before the time slot which is selected for the stov. stixy synchronous transfer interrupt depending on the dps bit in the corresponding tsdpxy register the synchronous transfer interrupt stixy is generated two (for dps = ? 0 ? ) or one (for dps = ? 1 ? ) bcl clock cycles after the selected time slot (tsdpxy.tss). 70 0 0 0 0 ack21 ack20 ack11 ack10 ackxy acknowledge synchronous transfer interrupt after a stixy interrupt the microcontroller has to acknowledge the interrupt by setting the corresponding ackxy bit. 0 = no activity is initiated 1 = sets the acknowledge bit ackxy for a stixy interrupt pef 82902 register description data sheet 151 2001-11-09 4.7.13 msti - mask synchronous transfer interrupt msti read/write address: 59 h value after reset: ff h 4.8 detailed monitor handler registers 4.8.1 mor - monitor receive channel mor read address: 5c h value after reset: ff h contains the monitor data received in the iom ? -2 monitor channel according to the monitor channel protocol. the monitor channel (0,1,2) can be selected by setting the monitor channel select bit mon_cr.mcs. 70 stov21 stov20 stov11 stov10 sti21 sti20 sti11 sti10 for the msti register the following logical states are applied: 0 = interrupt is not masked 1 = interrupt is masked stovxy mask synchronous transfer overflow xy mask bits for the corresponding stovxy interrupt bits. stixy synchronous transfer interrupt xy mask bits for the corresponding stixy interrupt bits. 70 pef 82902 register description data sheet 152 2001-11-09 4.8.2 mox - monitor transmit channel mox write address: 5c h value after reset: ff h contains the monitor data to be transmitted in iom ? -2 monitor channel according to the monitor channel protocol. the monitor channel (0,1,2) can be selected by setting the monitor channel select bit mon_cr.mcs 4.8.3 mosr - monitor interrupt status register mosr read address: 5d h value after reset: 00 h 70 70 mdr mer mda mab 0 0 0 0 mdr monitor channel data received 0 = inactive 1 = monitor channel data received mer monitor channel end of reception 0 = inactive 1 = monitor channel end of reception mda monitor channel data acknowledged the remote end has acknowledged the monitor byte being transmitted. 0 = inactive 1 = monitor channel data acknowledged mab monitor channel data abort pef 82902 register description data sheet 153 2001-11-09 4.8.4 mocr - monitor control register mocr read/write address: 5e h value after reset: 00 h 0 = inactive 1 = monitor channel data abort 70 mre mrc mie mxc 0 0 0 0 mre monitor receive interrupt enable 0 = monitor interrupt status mdr generation is masked. 1 = monitor interrupt status mdr generation is enabled. mrc mr bit control determines the value of the mr bit: 0 = mr is always ? 1 ? . in addition, the mdr interrupt is blocked, except for the first byte of a packet (if mre = 1). 1 = mr is internally controlled by the t-smint i according to monitor channel protocol. in addition, the mdr interrupt is enabled for all received bytes according to the monitor channel protocol (if mre = 1). mie monitor interrupt enable 0 = monitor interrupt status mer, mda, mab generation is masked 1 = monitor interrupt status mer, mda, mab generation is enabled mxc mx bit control determines the value of the mx bit: 0 = the mx bit is always ? 1 ? . 1 = the mx bit is internally controlled by the t-smint i according to monitor channel protocol. pef 82902 register description data sheet 154 2001-11-09 4.8.5 msta - monitor status register msta read address: 5f h value after reset: 00 h 4.8.6 mconf - monitor configuration register mconf write address: 5f h value after reset: 00 h 70 00000mac0tout mac monitor transmit channel active 0 = no data transmission in the monitor channel 1 = the data transmission in the monitor channel is in progress. tout time-out read-back value of the tout bit 0 = the monitor time-out function is disabled 1 = the monitor time-out function is enabled 70 0000000tout tout time-out 0 = the monitor time-out function is disabled 1 = the monitor time-out function is enabled pef 82902 register description data sheet 155 2001-11-09 4.9 detailed u-transceiver registers 4.9.1 opmode - operation mode register the op eration mode register determines the operating mode of the u-transceiver. opmode read* ) / write address: 60 h reset value: 00 h 4.9.2 ucir - c/i code read register via the u -transceiver c/i code r ead register a microcontroller can access the c/i code that is output from the state machine. ucir read address: 6d h reset value: 00 h 4.9.3 uciw - c/i code write register the u- transceiver c/i code w rite register allows a microcontroller to control the state of the u-transceiver. to enable this function bit uci in register opmode must be set to ? 1 ? before. 76543210 0uci000000 uci enable/disable p-control of c/i codes 0 = p control disabled - c/i codes are exchanged via iom ? -2 read access to register ucir by the p is still possible 1 = p control enabled - c/i codes are exchanged via ucir and uciw registers in this case, the according c/i-channel on iom ? -2 is idle ? 1111 ? 76543210 0 0 0 0 c/i code output pef 82902 register description data sheet 156 2001-11-09 uciw write address: 6e h reset value: 01 h 4.9.4 loop - loopback register the loop register controls local digital loopbacks of the u-transceiver. loop read* ) / write address: 70 h reset value: 08 h 76543210 0 0 0 0 c/i code input 76543210 00tran s u/iom 1 lbbd lb2 lb1 trans transparent/ non-transparent loopback in transparent mode data is both passed on and looped back, whereas in non-transparent mode data is not forwarded but substituted by 1s (idle code) and just looped back 0 = transparent mode 1 = non-transparent mode ? 1 ? s are sent on the iom ? -2 interface in the corresponding time-slot u/iom ? close lbbd, lb2, lb1 towards u or towards iom ? switch that selects whether loopback lb1, lb2 or lbbd is closed towards u or towards iom ? -2 the setting affects all test loops, lbbd, lb2 and lb1 an individual selection for lbbd, lb2, lb1 is not possible 0 = lb1, lb2, lbbd loops are closed towards iom ? 1 = lb1, lb2, lbbd loops are closed towards u pef 82902 register description data sheet 157 2001-11-09 4.9.5 rds - block error counter register see chapter 2.4.4.2 . rds read address: 72 h reset value: 00 h 4.9.6 istau - interrupt status register u-interface the i nterrupt sta tus register u -interface generates an interrupt for the unmasked interrupt flags. refer to chapter 2.4.8 for details on masking and clearing of interrupt flags. lbbd close complete loop (b1, b2, d) near the system interface ? the direction towards which the loop is closed is determined by bit u/iom ? ? the state machine has to be in state ? transparent ? first (e.g. by c/i = dt) before data is output on the u-interface 0 = complete loopback open 1 = complete loopback closed lb2 close loop b2 near the system interface ? the direction towards which the loop is closed is determined by bit u/iom ? ? the state machine has to be in state ? transparent ? first (e.g. by c/i = dt) before data is output on the u-interface 0 = loopback b2 open 1 = loopback b2 closed lb1 close loop b1 near the system interface ? the direction towards which the loop is closed is determined by bit u/iom ? ? the state machine has to be in state ? transparent ? first (e.g. by c/i = dt) before data is output on the u-interface 0 = loopback b1 open 1 = loopback b1 closed 76543210 block error counter value pef 82902 register description data sheet 158 2001-11-09 istau read address: 7a h reset value: 00 h 4.9.7 masku - mask register u-interface the interrupt mask register u -interface selectively masks each interrupt source in the istau register by setting the corresponding bit to ? 1 ? . masku read* ) / write address: 7b h reset value: ff h 76543210 0 ci rds 0 0 0 0 1 ms ci c/i code indication the ci interrupt is generated independently on opmode.uci 0 = inactive 1 = ci code change has occurred rds code violation occurred 0 = inactive 1 = code violation has occurred 1 ms start of a new frame on the u-interface useful for synchronization of register accesses by an external c 0 = inactive 1 = signals the start of a new frame on the u-interface 76543210 1 ci rds 1 1 1 1 1 ms pef 82902 register description data sheet 159 2001-11-09 4.9.8 fw_version fw _ v ersion register contains the firmware version number fw _ v ersion read address: 7d h reset value: 3e h bit 0..7 mask bits 0 = interrupt active 1 = interrupt masked 76543210 firmware version number pef 82902 electrical characteristics data sheet 160 2001-11-09 5 electrical characteristics 5.1 absolute maximum ratings esd integrity (according eia/jesd22-a114b (hbm)): 2 kv note: stress above those listed here may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. line overload protection the t-smint i is compliant to esd tests according to ansi / eos / esd-s 5.1-1993 (cdm), eia/jesd22-a114b (hbm) and to latch-up tests according to jedec eia / jesd78. from these tests the following max. input currents are derived ( table 33 ): parameter symbol limit values unit ambient temperature under bias t a -40 to 85 c storage temperature t stg ? 65 to 150 c maximum voltage on v dd v dd 4.2 v maximum voltage on any pin with respect to ground v s -0.3 to v dd + 3.3 (max. < 5.5) v table 33 maximum input currents test pulse width current remarks esd 100 ns 1.3 a 3 repetitions latch-up 5 ms +/-200 ma 2 repetitions, respectively dc -- 10 ma pef 82902 electrical characteristics data sheet 161 2001-11-09 5.2 dc characteristics table 34 s-transceiver characteristics v dd / v dda = 3.3 v +/- 5% ; v ss / v ssa = 0 v; t a = -40 to 85 c digital pins parameter symbol limit values unit test condition min. max. all input low voltage v il -0.3 0.8 v input high voltage v ih 2.0 5.25 v all except dd/du act ,lp2i mclk output low voltage v ol1 0.45 v i ol1 = 3.0 ma output high voltage v oh1 2.4 v i oh1 = 3.0 ma dd/du act ,lp2i mclk output low voltage v ol2 0.45 v i ol2 = 4.0 ma output high voltage (dd/du push-pull) v oh2 2.4 v i oh2 = 4.0 ma all input leakage current i li 10 a 0 v v in v dd output leakage current i lo 10 a 0 v v in v dd analog pins ain, bin input leakage current i li 30 a 0 v v in v d d pin parameter symbol limit values unit test condition min. typ. max. sx1,2 absolute value of output pulse amplitude (v sx2 - v sx1 ) v x 2.03 2.2 2.31 v r l = 50 ? sx1,2 s-transmitter output impedance z x 10 34 k ? see 1) 1) requirement itu-t i.430, chapter 8.5.1.1a): ? at all times except when transmitting a binary zero, the output impedance , in the frequency range of 2khz to 1 mhz, shall exceed the impedance indicated by the template in figure 11. the requirement is applicable with an applied sinusoidal voltage of 100 mv (r.m.s value) ? 0 see 2)3) sr1,2 s-receiver input impedance z r 10 100 k ? ? v dd = 3.3 v v dd = 0 v pef 82902 electrical characteristics data sheet 162 2001-11-09 table 35 u-transceiver characteristics 2) requirement itu-t i.430, chapter 8.5.1.1b): ? when transmitting a binary zero, the output impedance shall be > 20 ? . ? : must be met by external circuitry. 3) requirement itu-t i.430, chapter 8.5.1.1b), note: ? the output impedance limit shall apply for a nominal load impedance (resistive) of 50 ? . the output impedance for each nominal load shall be defined by determining the peak pulse amplitude for loads equal to the nominal value +/- 10%. the peak amplitude shall be defined as the the amplitude at the midpoint of a pulse. the limitation applies for pulses of both polarities. ? limit values unit min. typ. max. receive path signal / (noise + total harmonic distortion) 1) 1) test conditions: 1.4 vpp differential sine wave as input on ain/bin with long range (low, critical range). 65 2) 2) versions pef 8x913 with enhanced performance of the u-interface are tested with tightened limit values db dc-level at ad-output 45 50 55 % 3) 3) the percentage of the "1 "-values in the pdm-signal. threshold of level detect (measured between ain and bin with respect to zero signal) 10 23 mv peak input impedance ain/bin 80 k ? transmit path signal / (noise + total harmonic distortion) 4) 4) interpretation and test conditions: the sum of noise and total harmonic distortion, weighted with a low pass filter 0 to 80 khz, is at least 70 db below the signal for an evenly distributed but otherwise random sequence of +3, +1, -1, -3. 70 db common mode dc-level 1.61 1.65 1.69 v offset between aout and bout 35 mv absolute peak voltage for a single +3 or -3 pulse measured between aout and bout 5) 5) the signal amplitude measured over a period of 1 min. varies less than 1%. 2.42 2.5 2.58 v output impedance aout/bout: power-up power-down 0.8 3 1.5 6 ? ? pef 82902 electrical characteristics data sheet 163 2001-11-09 5.3 capacitances t a = 25 c, 3.3 v 5 % v ssa = 0 v, v ssd = 0 v, f c = 1 mhz, unmeasured pins grounded. 5.4 power consumption 5.5 supply voltages vdd d = + vdd 5% vdd a = + vdd 5% the maximum sinusoidal ripple on vdd is specified in the following figure: table 36 pin capacitances parameter symbol limit values unit remarks min. max. digital pads: input capacitance i/o capacitance c in c i/o 7 7 pf pf analog pads: load capacitance c l 3 pf pin ain, bin power consumption vdd=3.3 v, vss=0 v, inputs at vss/vdd, no led connected, 50% bin. zeros, no output loads except sx1,2 (50 ? 1) ) 1) 50 ? (2 x tr) on the s-bus. parameter limit values unit test condition min. typ. max. operational u and s enabled, iom -2 off 185 165 mw mw u: etsi loop 1 (0 m) u: etsi loop 2.(typical line) power down 15 mw pef 82902 electrical characteristics data sheet 164 2001-11-09 figure 60 maximum sinusoidal ripple on supply voltage 80 100 frequency / khz 10 100 mv (peak) 200 supply voltage ripple frequency ripple itd04269.vsd 60 pef 82902 electrical characteristics data sheet 165 2001-11-09 5.6 ac characteristics t a = -40 to 85 c, v dd = 3.3 v 5% inputs are driven to 2.4 v for a logical "1" and to 0.4 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and 0.8 v for a logical "0". the ac testing input/output waveforms are shown in figure 61 . figure 61 input/output waveform for ac tests parameter all output pins symbol limit values unit min max fall time 30 ns rise time 30 ns device under test c load =50 pf 2.4 0.45 2.0 0.8 0.8 2.0 test points its00621.vsd pef 82902 electrical characteristics data sheet 166 2001-11-09 5.6.1 iom ? -2 interface figure 62 iom ? -2 interface - bit synchronization timing figure 63 iom ? -2 interface - frame synchronization timing t 7 t 18 sds1,2 dcl du/dd (input) t 4 t 5 data valid last bit first bit du/dd (output) t 6 t 8 bit n bit n+1 du/dd (output) iom-timing.vsd fsc dcl t 9 t 10 bcl t 11 t 12 t 13 t 14 t 2 t 3 t 1 pef 82902 electrical characteristics data sheet 167 2001-11-09 note: at the start and end of a reset period, a frame jump may occur. this results in a dcl, bcl and fsc high time of min. 130 ns after this specific event. parameter iom ? -2 interface symbol limit values unit min typ max dcl period t 1 565 651 735 ns dcl high t 2 200 310 420 ns dcl low t 3 200 310 420 ns input data setup t 4 20 ns input data hold t 5 20 ns output data from high impedance to active (fsc high or other than first timeslot) t 6 100 ns output data from active to high impedance t 7 100 ns output data delay from clock t 8 80 ns fsc high t 9 50% of fsc cycle time ns fsc advance to dcl t 10 65 130 195 ns bcl high t 11 565 651 735 ns bcl low t 12 565 651 735 ns bcl period t 13 1130 1302 1470 ns fsc advance to bcl t 14 65 130 195 ns dcl, fsc rise/fall t 15 30 ns data out fall (c l = 50 pf, r = 2 k ? to v dd , open drain) t 16 200 ns data out rise/fall (c l = 50 pf, tristate) t 17 150 ns strobe signal delay t 18 120 ns pef 82902 electrical characteristics data sheet 168 2001-11-09 5.6.2 serial p interface figure 64 serial control interface parameter sci interface symbol limit values unit min max sclk cycle time t 1 200 ns sclk high time t 2 80 ns sclk low time t 3 80 ns cs setup time t 4 20 ns cs hold time t 5 10 ns sdr setup time t 6 15 ns sdr hold time t 7 15 ns sdx data out delay t 8 60 ns cs high to sdx tristate t 9 40 ns sclk to sdx active t 10 60 ns cs high to sclk t 11 10 ns sclk sdr cs sdx t 1 t 2 t 3 t 4 t 7 t 10 t 8 t 6 t 9 t 11 t 5 sci_timing.vsd pef 82902 electrical characteristics data sheet 169 2001-11-09 5.6.3 parallel p interface siemens/intel bus mode figure 65 microprocessor read cycle figure 66 microprocessor write cycle figure 67 multiplexed address timing ad0 - ad7 rd x cs data t rr t rd t ri itt00712.vsd t df t dh ad0 - ad7 wr x cs data t ww t dw t wi t wd itt00713.vsd t la wr x cs or rd x cs ad0 - ad7 address t aa t al t als t ad ale itt00714.vsd pef 82902 electrical characteristics data sheet 170 2001-11-09 figure 68 non-multiplexed address timing motorola bus mode figure 69 microprocessor read timing figure 70 microprocessor write cycle t as t ah wr x cs or rd x cs a0 - a6 address itt009661.vsd d0 - d7 cs x ds r / w t rr t rd t ri t rwd t dsd itt00716.vsd data t df t dh d0 - d7 cs x ds data t ww t dw t wi t wd r / w t rwd t dsd itt09679.vsd pef 82902 electrical characteristics data sheet 171 2001-11-09 figure 71 non-multiplexed address timing microprocessor interface timing parameter symbol limit values unit min. max. ale pulse width t aa 20 ns address setup time to ale t al 10 ns address hold time from ale t la 10 ns address latch setup time to wr , rd t als 10 ns address setup time t as 10 ns address hold time t ah 10 ns ale guard time t ad 10 ns ds delay after r/w setup t dsd 10 ns rd pulse width t rr 80 ns data output delay from rd t rd 80 ns data hold from rd t dh 0ns data float from rd t df 25 ns rd control interval 1) t ri 70 ns w pulse width t ww 60 ns data setup time to w x cs t dw 10 ns data hold time w x cs t wd 10 ns w control interval t wi 70 ns r/w hold from cs x ds inactive t rwd 10 ns t as t ah a0 - a6 cs x ds itt09662.vsd address pef 82902 electrical characteristics data sheet 172 2001-11-09 1) control interval: t ri ' is minimal 70ns for all registers except istau, febe and nebe. however, the time between two consecutive read accesses to one of the registers istau, febe or nebe, respectively, must be longer than 330ns. this does not limit t ri of read sequences, which involve intermediate read access to other registers, as for instance: istau -(t ri )- ista -(t ri )- istah -(t ri )- istau. pef 82902 electrical characteristics data sheet 173 2001-11-09 5.6.4 reset table 37 reset input signal characteristics figure 72 reset input signal parameter symbol limit values unit test conditions min. typ. max. length of active low state t rst 4 ms power on the 4 ms are assumed to be long enough for the oscillator to run correctly 2 x dcl clock cycles + 400 ns after power on delay time for c access after rst rising edge t c 500 ns t rst rst itd09823.vsd t c pef 82902 electrical characteristics data sheet 174 2001-11-09 5.6.5 undervoltage detection characteristics figure 73 undervoltage control timing table 38 parameters of the uvd/por circuit v dd = 3.3 v 5 %; v ss = 0 v; t a = -40 to 85 c parameter symbol limit values unit test condition min. typ. max. detection threshold 1) v det 2.7 2.8 2.92 v v dd = 3.3 v 5 % hysteresis v hys 30 90 mv max. rising/falling v dd edge for activation/ deactivation of uvd dv dd /dt 0.1 v/s max. rising v dd for power-on 2) 0.1 v/ ms min. operating voltage v ddmin 1.5 v v dd v ddmin v det t t rsto t act t act t deact t deact v hys vdddet.vsd pef 82902 electrical characteristics data sheet 175 2001-11-09 delay for activation of rsto t act 10 s delay for deactivation of rsto t deact 64 ms 1) the detection threshold v det is far below the specified supply voltage range of analog and digital parts of the t-smint ? . therefore, the board designer must take into account that a range of voltages is existing, where neither performance and functionality of the t-smint ? are guaranteed, nor a reset is generated. 2) if the integrated power-on reset of the t-sminti is selected (vdddet = ? 0 ? ) and the supply voltage v dd is ramped up from 0v to 3.3v +/- 5%, then the t-sminti is kept in reset during v ddmin < v dd < v det + v hys . v dd must be ramped up so slowly that the t-sminti leaves the reset state after the oscillator circuit has already finished start-up. the start-up time of the oscillator circuit is typically in the range between 3ms and 12ms. v dd = 3.3 v 5 %; v ss = 0 v; t a = -40 to 85 c parameter symbol limit values unit test condition min. typ. max. pef 82902 package outlines data sheet 176 2001-11-09 6 package outlines plastic package, p-mqfp-64 (metric quad flat package) pef 82902 package outlines data sheet 177 2001-11-09 plastic package, p-tqfp-64 (thin quad flat package) pef 82902 appendix: differences between q- and t-smint?i data sheet 178 2001-11-09 7 appendix: differences between q- and t-smint i the q- and t-smint i have been designed to be as compatible as possible. however, some differences between them are unavoidable due to the different line codes 2b1q and 4b3t used for data transmission on the u k0 line. especially the pin compatibility between q- and t-smint i allows for one single pcb design for both series with only some mounting differences. the c software can distinguish between the q- and t-series by reading the hardware design number via the iom -2 (monitor channel identification command) or the c interface (register id.design), respectively (see table 39 ). the following chapter summarizes the main differences between the q- and t-smint i. table 39 design number design number q-smint i: 2b1q t-smint i: 4b3t version version 1.3: ? 000 001 ? version 1.1: ? 100 000 ? pef 82902 appendix: differences between q- and t-smint?i data sheet 179 2001-11-09 7.1 pinning 7.1.1 pin definitions and functions 7.1.2 led pin act the 4 led states (off, fast flashing, slow flashing, on), which can be displayed with pin act , are slightly different for q- and t-smint i (see table 41 ). this adoption guarantees full compliance of t-smint i to the new int specification ts 0284/96. note: * denotes the duty cycle ?high? : ?low?. table 40 pin definitions and functions pin t/mqfp-64 q-smint i: 2b1q t-smint i: 4b3t 16 metallic termination input (mti) tie to ? 1 ? 55 power status (primary) (ps1) tie to ? 1 ? 41 power status (secondary) (ps2) tie to ? 1 ? table 41 act states led states pin act q-smint i: 2b1q t-smint i: 4b3t off v dd v dd fast flashing 8hz (1 : 1)* 2hz (1 : 1)* slow flashing 1hz (1 : 1)* 1hz (3 : 1)* on gnd gnd pef 82902 appendix: differences between q- and t-smint?i data sheet 180 2001-11-09 7.2 u-transceiver 7.2.1 u-interface conformity table 42 related documents to the u-interface q-smint i: 2b1q t-smint i: 4b3t etsi: ts 102 080 conform to annex a compliant to 10 ms interruptions conform to annex b ansi: t1.601-1998 (revision of ansi t1.601- 1992) conform mlt input and decode logic not required cnet: st/laa/elr/dnp/ 822 conform not required rc7355e conform not required ftz-richtlinie 1 tr 220 not required conform ftz ts 0284/96 ? intelligenter netzabschluss (int) ? m ? rz 2001 not required conform pef 82902 appendix: differences between q- and t-smint?i data sheet 181 2001-11-09 7.2.2 u-transceiver state machines figure 74 ntc-q compatible state machine q-smint i: 2b1q sn3/sn3t act=1/0 pend.deact. s/t . . . . . synchronized 2 eq-training wait for sf dr sn1 dr . sn3/sn3t sn3t sn3/sn3t dc sn0 pending timing . sn0 . deactivated dc sn0 alerting tn reset dr pu iom awaked sn0 tn . alerting 1 ec-training 1 . sn1 ec-training al dc dc ar dc ec-training wait for sf al analog loop back sn3 sn3t act=0 act=0 sn3/sn3t act=1/0 pend.deact. u dc pend receive res. sn0 error s/t transparent wait for act ar/arl ar/arl ai/ail act=0 act=1 act=0 act=1 act=0 synchronized 1 dc dr tim ar or tl t14s t14s di arl t12s lsec or t12e bbd1 & sfd t11e t12s lsec or t12e bbd0 & fd t20e & bbd0 & sfd dc dc lof t1s, t11s ei1 ar or tl t11e t12s dea=0 lsue uoa=1 uoa=1 ? lsue dea=0 di ar/arl dea=0 lsue dr receive reset sn0 . yes no al act=1 act=0 act=1 & al lof t13s dea=1 uoa=0 uoa=0 dea=0 lsue uoa=0 dea=0 lsue lof lof el1 act=0 dea=0 uoa=0 lsue t7s tl t7e & di lsu or ( /lof & t13e ) t7s lsu t14e t14s tl sn3/sn3t sn3/sn3t sn2 sn0 sn1 . di lsue or t1e di el1 lof lsue or t1e t1s, t11s . . lof di & nt-auto sp test dr . any state ssp or c/i= 'ssp' di lof 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) 3) 3) any state dt or c/i='dt' any state pin-rst or c/i= 'res' t20s t1s t11s dc pu pef 82902 appendix: differences between q- and t-smint?i data sheet 182 2001-11-09 figure 75 simplified state machine q-smint i: 2b1q sn3/sn3t act=1/0 pend.deact. s/t . . . . . synchronized 2 eq-training wait for sf dr sn1 dr . sn3/sn3t sn3t sn3/sn3t dc sn0 pending timing . sn0 . deactivated dc sn0 alerting tn reset dr pu iom awaked sn0 tn . alerting 1 ec-training 1 . sn1 ec-training al ar ec-training wait for sf al analog loop back sn3 sn3t act=0 act=0 sn3/sn3t act=1/0 pend.deact. u pend receive res. sn0 error s/t transparent wait for act ar/arl ar/arl ai/ail act=0 act=1 act=0 act=1 act=0 synchronized 1 dr tim ar or tl t14s t14s di arl t12s lsec or t12e bbd1 & sfd t11e t12s lsec or t12e bbd0 & fd t20e & bbd0 & sfd lof t1s, t11s ar or tl t11e t12s dea=0 lsue uoa=1 uoa=1 ? lsue dea=0 di ar/arl dea=0 lsue dr receive reset sn0 . yes no al act=1 act=0 act=1 & al lof t13s dea=1 uoa=0 uoa=0 dea=0 lsue uoa=0 dea=0 lsue lof lof el1 act=0 dea=0 uoa=0 lsue t7s tl t7e & di lsu or ( /lof & t13e ) t7s lsu t14e t14s tl sn3/sn3t sn3/sn3t sn2 sn0 sn1 . di lsue or t1e di el1 lof lsue or t1e t1s, t11s . . lof sp test dr . any state ssp or c/i= 'ssp' di lof 1) 1) 1) 1) 1) 1) 2) 2) 2) 2) 3) 3) any state dt or c/i='dt' any state pin-rst or c/i= 'res' t20s tim pu pu pu pu pu or tim or tim dr t7e & tim dr dr dr t1s t11s pef 82902 appendix: differences between q- and t-smint?i data sheet 183 2001-11-09 figure 76 iec-t/ntc-t compatible state machine t-smint i: 4b3t both the q- and the t-smint i u-transceiver can be controlled via state machines, which are compatible to those defined for the old nt generation intc-q and ntc-t. additionally, the q-smint i possesses a newly defined, so called ? simplified ? state machine. this simplified state machine can be used optionally instead of the intc-q compatible state machine and eases the u-transceiver control by software. such a simplified state machine is not available for the t-smint i. awr any state awr dt awr awake signal sent rsy ack. sent / received rsy u0, da ar awt start awaking uk0 rsy iom awaked dc t6e awt sending awake-ack. rsy tim awr deactivated dc deactivating dc ar di awr t05e u0 t6s t05s t6s u1w u0 t13s u0 u1w t13s t05s t13s u0 u0 res ssp or ltd (di & t05e) t05s nt_sm_4b3t_cust.emf di t6s rsy loss of framing u0 u0 u0 u0 pend. deactivation dr u0 (u0 & t12e) u2 t12s t13e ai u4h ar / arl sbc synchronizing u1 ar / arl wait for info u4h u3 transparent ai / ail u5 lof lof lof u0 t05s reset dr u0 di test dr sp / u0 synchronizing rsy u1a pef 82902 appendix: differences between q- and t-smint?i data sheet 184 2001-11-09 7.2.3 command/indication codes table 43 c/i codes code q-smint i: 2b1q t-smint i: 4b3t in out in out 0000 tim dr tim dr 0001 res ??? 0010 ???? 0011 ?? ltd ? 0100 ei1 ei1 ? rsy 0101 ssp ? ssp ? 0110 dt ? dt ? 0111 ? pu ?? 1000 ar ar ar ar 1001 ???? 1010 arl arl ? arl 1011 ???? 1100 ai ai ai ai 1101 ?? res ? 1110 ? ail ? ail 1111 di dc di dc pef 82902 appendix: differences between q- and t-smint?i data sheet 185 2001-11-09 7.2.4 interrupt structure figure 77 interrupt structure u-transceiver q-smint i: 2b1q a1 a2 i8 aib uoa m46 m45 m44 sco dea act mlt ci febe/ nebe m56 m4 eoc 6ms 12ms mlt ci febe/ nebe m56 m4 eoc 6ms 12ms 0 ms2 ms1 nebe m61 m52 m51 febe m56r m4r m4rmask mfilt opmode.mlt crc, tll, no filtering tll, chg, no filtering mfilt eocr istau masku 0 7 0 7 0 7 crc, tll, no filtering 15 0 11 + mfilt + reserved interr_u_q2.vsd u ista mask int ucir 0 7 c/i c/i c/i c/i 0 7 pef 82902 appendix: differences between q- and t-smint?i data sheet 186 2001-11-09 figure 78 interrupt structure u-transceiver t-smint i: 4b3t u s ... ... ... ... ... ... ista mask int intstruct_4b3t.emf 0 ci 0 0 1ms 1 ci 1 1 1ms 0 7 ucir 0 7 0 0 0 0 c/i c/i c/i c/i rds rds 0 0 1 1 istau masku pef 82902 appendix: differences between q- and t-smint?i data sheet 187 2001-11-09 7.2.5 register summary u-transceiver u-interface registers q-smint i: 2b1q name 76543210addrr/wres opmode 0 uci febe mlt 0ci_ sel 0060 h r*/w 14 h mfilt m56 filter m4 filter eoc filter 61 h r*/w 14 h reserved 62 h eocr 0000a1a2a3d/m63 h r0f i1 i2 i3 i4 i5 i6 i7 i8 64 h ff h eocw 0000a1a2a3d/m65 h w01 h i1 i2 i3 i4 i5 i6 i7 i8 66 h 00 h m4rmask m4 read mask bits 67 h r*/w 00 h m4wmask m4 write mask bits 68 h r*/w a8 h m4r verified m4 bit data of last received superframe 69 h rbe h m4w m4 bit data to be send with next superframe 6a h r*/w be h m56r 0 ms2 ms1 nebe m61 m52 m51 febe 6b h r1f h m56w 1111m61m52m51febe6c h wff h ucir 0000 c/i code output 6d h r00 h uciw 0000 c/i c ode input 6e h w01 h test 0000ccrc+-1 tones 040khz6f h r*/w 00 h loop 0 dlb trans u/iom 1 lbbd lb2 lb1 70 h r*/w 08 h febe febe counter value 71 h r00 h nebe nebe counter value 72 h r00 h reserved 73 h - 79 h pef 82902 appendix: differences between q- and t-smint?i data sheet 188 2001-11-09 istau mlt ci febe/ nebe m56 m4 eoc 6ms 12ms 7a h r00 h masku mlt ci febe/ nebe m56 m4 eoc 6ms 12ms 7b h r*/w ff h reserved 7c h fw_ version fw version number 7d h r6x h reserved 7e h - 7f h name 76543210addrr/wres pef 82902 appendix: differences between q- and t-smint?i data sheet 189 2001-11-09 u-interface registers t-smint i: 4b3t name 76543210addrr/wres opmode 0 uci 0 0 0 0 0 060 h r*/w 00 h reserved 61 h - 6c h ucir 0 0 0 0 c/i code output 6d h r00 h uciw 0 0 0 0 c/i code input 6e h w01 h reserved 6f h loop 0 0 transu/iom 1 lbbd lb2 lb1 70 h r*/w 08 h reserved 71 h rds block error counter value 72 h r00 h reserved 73 h - 79 h istau 0 ci rds 0 0 0 0 1 ms 7a h r00 h masku 1 ci rds 1 1 1 1 1 ms 7b h r*/w ff h reserved 7c h fw_ version fw version number 7d h r3x h reserved 7e h - 7f h pef 82902 appendix: differences between q- and t-smint?i data sheet 190 2001-11-09 7.3 external circuitry the external circuitry of the q- and t-smint i is equivalent; however, some external components of the u-transceiver hybrid must be dimensioned different for 2b1q and 4b3t. all information on the external circuitry is preliminary and may be changed in future documents. figure 79 external circuitry q- and t-smint i note: the necessary protection circuitry is not displayed in figure 79 . table 44 dimensions of external components component q-smint i: 2b1q t-smint i: 4b3t transformer: ratio main inductivity 1:2 14.5 mh 1:1.6 7.5 mh resistance 1.3 k ? 1.75 k ? resistance 1.0 k ? 1.0 k ? resistance 9.5 ? 25 ? capacitor c 27 nf 15 nf r ptc and r comp 2r ptc + 8r comp = 40 ? n 2 (2r comp + r b ) + r l = 20 ? loop aout bout ain bin n c r t r4 r comp r comp r ptc r ptc >1 r3 r3 r4 r t extcirc_u_q2_exthybrid.emf pef 82902 index data sheet 191 2001-11-09 8index a absolute maximum ratings 160 address space 114 b block diagram 6 block error counter 65 c c/i channel detailed registers 124 functional description 49 c/i codes s-transceiver 85 u-transceiver 66 controller data access (cda) 30 d dc characteristics 161 d-channel access control functional description 51 state machine 55 differences between q- and t-smint 178 e external circuitry s-transceiver 110 f features 3 i identification via monitor channel 47 via register access 139 interrupts 114 iom ? -2 interface ac characteristics 166 activation/deactivation 57 detailed registers 140 frame structure 27 functional description 27 l layer 1 activation / deactivation 96 loopbacks 104 led pins 12 line overload protection 160 m maintenance channel 63 microcontroller clock generation 23 microcontroller interfaces interface selection 16 parallel microcontroller interface 21 serial control interface (sci) 16 monitor channel detailed registers 151 error treatment 45 functional description 41 handshake procedure 41 interrupt logic 48 time-out procedure 48 o oscillator circuitry 113 p package outlines 176 parallel microcontroller interface ac-characteristics 169 functional description 21 pin configuration 5 pin definitions and functions 7 power consumption 163 power supply blocking 108 power-on reset 26, 174 r register summary 116 reset generation 23 pef 82902 index data sheet 192 2001-11-09 input signal characteristics 173 power-on reset 26, 174 under voltage detection 26, 174 s s/q channels 81 scrambler / descrambler 66 serial control interface (sci) ac-characteristics 168 functional description 16 serial data strobe signal 40 stop/go bit handling 53 s-transceiver detailed registers 128 functional description 79 state machine, lt-s 91 state machine, nt 87 supply voltages 163 synchronous transfer 36 system integration 13 t test modes 12 tic bus handling 52 u u-interface hybrid 108 under voltage detection 26, 174 u-transceiver 4b3t frame structure 59 detailed registers 155 functional description 59 state machine nt 67 w watchdog timer 25 http://www.infineon.com published by infineon technologies ag infineon goes for business excellence ? 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